Person:
Prieto Matías, Manuel

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First Name
Manuel
Last Name
Prieto Matías
URI
https://hdl.handle.net/20.500.14352/78600
Affiliation
Universidad Complutense de Madrid
Faculty / Institute
Informática
Department
Arquitectura de Computadores y Automática
Area
Arquitectura y Tecnología de Computadores
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UCM identifierORCIDScopus Author IDWeb of Science ResearcherIDDialnet IDGoogle Scholar ID

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    2-D wavelet transform enhancement on general-purpose microprocessors: memory hierarchy and SIMD parallelism exploitation
    (High performance computing - HIPC 2002, proceedings, 2002) Chaver Martínez, Daniel Ángel; Tenllado van der Reijden, Christian; Piñuel Moreno, Luis; Prieto Matías, Manuel; Tirado Fernández, Francisco
    This paper addresses the implementation of a 2-D Discrete Wavelet Transform on general-purpose microprocessors, focusing on both memory hierarchy and SIMD parallelization issues. Both topics are somewhat related, since SIMD extensions are only useful if the memory hierarchy is efficiently exploited. In this work, locality has been significantly improved by means of a novel approach called pipelined computation, which complements previous techniques based on loop tiling and non-linear layouts. As experimental platforms we have employed a Pentium-III (P-III) and a Pentium-4 (P-4) microprocessor. However, our SIMD-oriented tuning has been exclusively performed at source code level. Basically, we have reordered some loops and introduced some modifications that allow automatic vectorization. Taking into account the abstraction level at which the optimizations are carried out, the speedups obtained on the investigated platforms are quite satisfactory, even though further improvement can be obtained by dropping the level of abstraction (compiler intrinsics or assembly code).
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    A power-efficient and scalable load-store queue design
    (Integrated circuit and system design: power and timing modeling, optimization and simulation, 2005) Castro, F.; Chaver Martínez, Daniel Ángel; Piñuel Moreno, Luis; Prieto Matías, Manuel; Huang, M. C.; Tirado Fernández, Francisco
    The load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.