Person:
Gómez Pérez, José Ignacio

Profile Picture
First Name
José Ignacio
Last Name
Gómez Pérez
URI
https://hdl.handle.net/20.500.14352/78649
Affiliation
Universidad Complutense de Madrid
Faculty / Institute
Informática
Department
Arquitectura de Computadores y Automática
Area
Arquitectura y Tecnología de Computadores
Identifiers
UCM identifierORCIDScopus Author IDDialnet IDGoogle Scholar ID

Filters

2019 - 201912020 - 20241
Reset filters

Settings

Author: Bueno Mora, Nicolás ×

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    Improving the representativeness of simulation intervals for the cache memory system
    (IEEE Access, 2024) Bueno Mora, Nicolás; Castro Rodríguez, Fernando; Piñuel Moreno, Luis; Gómez Pérez, José Ignacio; Catthor, Francky
    Accurate simulation techniques are indispensable to efficiently propose new memory or architectural organizations. As implementing new hardware concepts in real systems is often not feasible, cycle-accurate simulators employed together with certain benchmarks are commonly used. However, detailed simulators may take too much time to execute these programs until completion. Therefore, several techniques aimed at reducing this time are usually employed. These schemes select fragments of the source code considered as representative of the entire application’s behaviour–mainly in terms of performance, but not plenty considering the behaviour of cache memory levels–and only these intervals are simulated. Our hypothesis is that the different simulation windows currently employed when evaluating microarchitectural proposals, especially those involving the last level cache (LLC), do not reproduce the overall cache behaviour during the entire execution, potentially leading to wrong conclusions on the real performance of the proposals assessed. In this work, we first demonstrate this hypothesis by evaluating different cache replacement policies using various typical simulation approaches. Consequently, we also propose a simulation strategy, based on the applications’ LLC activity, which mimics the overall behaviour of the cache much closer than conventional simulation intervals. Our proposal allows a fairer comparison between cache-related approaches as it reports, on average, a number of changes in the relative order among the policies assessed – with respect to the full simulation – more than 30% lower than that of conventional strategies, maintaining the simulation time largely unchanged and without losing accuracy on performance terms, especially for memory-intensive applications.
  • Thumbnail Image
    Item
    A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs
    (2019) Evenblij, Timmon; Komalan, Manu Perumkunnil; Catthoor, Franky; Sakhare, Sushil; Debacker, Peter; Kar, Gouri; Furnemont, Arnaud; Bueno Mora, Nicolás; Gómez Pérez, José Ignacio; Tenllado Van Der Reijden, Christian Tomás; IEEE
    Spin Transfer Torque Magnetic RAM (STT-MRAM) is being extensively considered as a promising replacement for Last Level Caches (LLC), due to its high density, low leakage and non-volatility. However, writes to STT-MRAM are energy intensive and have a high latency. While the high dynamic energy consumption during writes can be compensated by the low static energy consumption, the high latency results in performance degradation. This work shows that in contrast to SRAM-based LLCs, the performance degradation for STT-MRAM is primarily due to bank contention, when trying to satisfy a read request while the bank is being written. We holistically explore the effects of cache banking and cache contention on energy and performance in the LLC of mobile multicore systems, with in-order cores or with out-of-order cores. The detail of the analysis is enabled by highly accurate cache models, based on a 28nm SRAM industry compiler, and an in-house developed STT-MRAM compiler, which generates full STT-MRAM macro designs with silicon-validated MTJ stack and complete parasitic extraction at the 28nm node. Our results show that there is a clear difference in the energy-performance optimal banking configuration between STT-MRAM caches and SRAM caches. These low contention STT-MRAM cache designs with the optimal number of banks save at least 60% cache energy while losing at most single digit percentages in system performance compared to SRAM cache designs. This show an increased potential of using STT-MRAM as a replacement for SRAM in an LLC.