Person:
Gómez Pérez, José Ignacio

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First Name
José Ignacio
Last Name
Gómez Pérez
URI
https://hdl.handle.net/20.500.14352/78649
Affiliation
Universidad Complutense de Madrid
Faculty / Institute
Informática
Department
Arquitectura de Computadores y Automática
Area
Arquitectura y Tecnología de Computadores
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2022 - 20233
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Author: Catthoor, Francky × End date: 2024 ×

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Now showing 1 - 3 of 3
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    COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
    (Journal of Systems Architecture, 2023) Marinelli, Tommaso; Gómez Pérez, José Ignacio; Tenllado Van Der Reijden, Christian Tomás; Catthoor, Francky
    The growing trend of pervasive computing has consolidated the everlasting need for power efficient devices. The conventional cache subsystem of general-purpose CPUs, while being able to adapt to many use cases, suffers from energy inefficiencies in some scenarios. It is well-known by now in the academic literature that the utilization of a scratchpad memory (SPM) can help reducing the overall energy consumption of embedded systems. This work proposes a hybrid cache-SPM architecture with support logic for semi-transparent data management and spatial locality improvement. Selected data are transferred and stored in the SPM in a compact form using dynamic layout transformation. As a second major contribution, we introduce a methodology to identify memory access sequences that make an inefficient use of the cache, marking them as candidates to be moved to an SPM of constrained space. The methodology does not require access to the source code of the target applications, relying on binary instrumentation and offline profiling. The resulting mapping policies have been tested on a simulated system, showing a mean memory dynamic energy reduction of 43% and a mean speed gain of 13% with a representative benchmark set.
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    Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices
    (ACM Transactions on Embedded Computing Systems (TECS), 2022) Komalan, Manu; Gupta, Mohit; Catthoor, Francky; Gómez Pérez, José Ignacio; Marinelli, Tommaso; Tenllado Van Der Reijden, Christian Tomás
    As the technology scaling advances, limitations of traditional memories in terms of density and energy become more evident. Modern caches occupy a large part of a CPU physical size and high static leakage poses a limit to the overall efficiency of the systems, including IoT/edge devices. Several alternatives to CMOS SRAM memories have been studied during the past few decades, some of which already represent a viable replacement for different levels of the cache hierarchy. One of the most promising technologies is the spin-transfer torque magnetic RAM (STT-MRAM), due to its small basic cell design, almost absent static current and nonvolatility as an added value. However, nothing comes for free, and designers will have to deal with other limitations, such as the higher latencies and dynamic energy consumption for write operations compared to reads. The goal of this work is to explore several microarchitectural parameters that may overcome some of those drawbacks when using STT-MRAM as last-level cache (LLC) in embedded devices. Such parameters include: number of cache banks, number of miss status handling registers (MSHRs) and write buffer entries, presence of hardware prefetchers. We show that an effective tuning of those parameters may virtually remove any performance loss while saving more than 60% of the LLC energy on average. The analysis is then extended comparing the energy results from calibrated technology models with data obtained with freely available tools, highlighting the importance of using accurate models for architectural exploration.
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    Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM
    (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022) Mayahinia, Mahta; Tahoori, Mehdi; Komalan, Manu Perumkunnil; Zahedmanesh, Houman; Croes, Kristof; Marinelli, Tommaso; Gómez Pérez, José Ignacio; Evenblij, Timon; Kar, Gouri Sankar; Catthoor, Francky
    Electromigration (EM) has been known as a reliability threatening factor for back-end-of-the-line interconnects. Spin Transfer Torque Magnetic RAM (STT-MRAM) is an emerging non-volatile memory that has gained a lot of attention in recent years. However, relatively large operational current magnitude is a challenge for this technology, and hence, EM can be a potential reliability concern, even for the signal lines of this memory. A workload-aware EM modeling needs to capture time-dependent current density in the memory signal lines, and to be able to predict the effect of the EM phenomenon on the interconnect for its entire lifetime. In this work, we present methods to effectively model the workload-dependent EM-induced mean time to failure (MTTF) in typical STT-MRAM arrays under a variety of realistic workloads. This allows performing the design space exploration to co-optimize reliability and other design metrics.