Person: San Andrés Serrano, Enrique
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First Name
Enrique
Last Name
San Andrés Serrano
Affiliation
Universidad Complutense de Madrid
Faculty / Institute
Ciencias Físicas
Department
Estructura de la Materia, Física Térmica y Electrónica
Area
Electrónica
Identifiers
68 results
Search Results
Now showing 1 - 10 of 68
Item Inversion charge study in TMO hole-selective contact based solar cells(IEEE Journal of Photovoltaics, 2023) García Hernansanz, Rodrigo; Pérez Zenteno, F.; Duarte Cano, S.; Caudevilla Gutiérrez, Daniel; Algaidy, S.; García Hemme, Eric; Olea Ariza, Javier; Pastor Pastor, David; Prado Millán, Álvaro Del; San Andrés Serrano, Enrique; Martil De La Plaza, Ignacio; Ros, E.; Puigdollers, J.; Ortega, P.; Voz, C.In this article, we study the effect of the inversion charge ( Q _inv ) in a solar cell based on the hole-selective characteristic of substoichiometric molybdenum oxide (MoO_x ) and vanadium oxide (VO_x ) deposited directly on n-type silicon. We measure the capacitance–voltage ( C – V ) curves of the solar cells at different frequencies and explain the results taking into account the variation of the space charge and the existence of Q_inv in the c-Si inverted region. The high-frequency capacitance measurements follow the Schottky metal–semiconductor theory, pointing to a low inversion charge influence in these measurements. However, for frequencies lower than 20 kHz, an increase in the capacitance is observed, which we relate to the contribution of the inversion charge. In addition, applying the metal–semiconductor theory to the high-frequency measurements, we have obtained the built-in voltage potential and show new evidence about the nature of the conduction process in this structure. This article provides a better understanding of the transition metal oxide/n-type crystalline silicon heterocontact.Item Time-dependent dielectric breakdown on subnanometer EOT nMOS FinFETs(IEEE Transactions on Device and Materials Reliability, 2012) Feijoo. Pedro Carlos; Kauerauf. Thomas; Toledano-Luque. María; Togo. Misuhiro; San Andrés Serrano, Enrique; Groeseneken. Guido.In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-kappa and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around 10(-8) cm(2), implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents.Item Anomalous thermal oxidation of gadolinium thin films deposited on silicon by high pressure sputtering(Microelectronic Engineering, 2011) María Ángela, Pampillón.; Feijoo, Pedro Carlos; San Andrés Serrano, Enrique; Lucía Mulas, María Luisa; Prado Millán, Álvaro Del; Toledano-Luque, MaríaThin gadolinium metallic layers were deposited by high-pressure sputtering in pure Ar atmosphere. Subsequently, in situ thermal oxidation was performed at temperatures ranging from 150 to 750 °C. At an oxidation temperature of 500 °C the films show a transition from monoclinic structure to a mixture of monoclinic and cubic. Regrowth of interfacial SiOx is observed as temperature is increased, up to 1.6 nm for 750 °C. This temperature yields the lowest interface trap density, 4 × 1010 eV−1 cm−2, but the effective permittivity of the resulting dielectric is only 7.4. The reason of this low value is found on the oxidation mechanism, which yields a surface with located bumps. These bumps increase the average thickness, thus reducing the capacitance and therefore the calculated permittivity.Item Nano-laminate vs. direct deposition of high permittivity gadolinium scandate on silicon by high pressure sputtering(Thin Solid Films, 2015) Feijoo, P.C.; Pampillón Arce, María Ángela; San Andrés Serrano, Enrique; Fierro, J.L.G.In this work we use the high pressure sputtering technique to deposit the high permittivity dielectric gadolinium scandate on silicon substrates. This nonconventional deposition technique prevents substrate damage and allows for growth of ternary compounds with controlled composition. Two different approaches were assessed: the first one consists in depositing the material directly from a stoichiometric GdScO_(3) target; in the second one, we anneal a nano-laminate of <0.5 nm thick Gd_(2)O_(3) and Sc_(2)O_(3) films in order to control the composition of the scandate. Metal-insulator-semiconductor capacitors were fabricated with platinum gates for electrical characterization. Accordingly, we grow a Gd-rich Gd_(2-x)Sc_(x)O_(3) film that, in spite of higher leakage currents, presents a better effective relative permittivity of 21 and lower density of defects.Item High pressure sputtering for kigh-k dielectric deposition. Is it worth trying?(ECS Transactions, 2014) San Andrés Serrano, Enrique; Feijoo. Pedro Carlos; Pampillón. María Ángela; Lucía Mulas, María Luisa; Prado Millán, Álvaro DelOur research group studies the deposition of high permittivity dielectrics by a non-standard method: high-pressure sputtering. The dielectrics studied here are gadolinium scandate deposited from dielectric targets, and gadolinium oxide deposited from a metallic target, with an in situ plasma oxidation. The stoichiometric gadolinium scandate presents a slight permittivity boost after annealing, but with gadolinium-rich scandate (grown with an annealing of a nanolaminate) the dielectric shows a high effective permittivity of 21 and no noticeable SiO2 layer at the interface with Si. On the other hand, the stacks fabricated with the metallic Gd target have a SiO2 interface less than 0.7 nm thick that can be further reduced by scavenging with Ti gates. In fact, this scavenging effect is also demonstrated for the first time with indium phosphide substrates, obtaining a low capacitance equivalent thickness of only 2.1 nm.Item Electronic transport properties of Ti-supersaturated Si processed by rapid thermal annealing or pulsed-laser melting(Semiconductor Science and Technology, 2022) Olea Ariza, Javier; González Díaz, Germán; Pastor Pastor, David; García Hemme, Eric; Caudevilla Gutiérrez, Daniel; Algaidy, S; Pérez-Zenteno, F.; Duarte-Cano, S.; García Hernansanz, Rodrigo; Prado Millán, Álvaro Del; San Andrés Serrano, Enrique; Martil De La Plaza, IgnacioIn the scope of supersaturated semiconductors for infrared detectors, we implanted Si samples with Ti at high doses and processed them by rapid thermal annealing (RTA) to recover the crystal quality. Also, for comparative purposes, some samples were processed by pulsed-laser melting. We measured the electronic transport properties at variable temperatures and analyzed the results. The results indicate that, for RTA samples, surface layers with a high Ti concentration have negligible conductivity due to defects. In contrast, the implantation tail region has measurable conductivity due to very high electron mobility. This region shows the activation of a very shallow donor and a deep donor level. While deep levels have been previously reported for Ti in Si, such a shallow level has never been measured, and we suggest that it originates from Ti-Si complexes. Finally, a decoupling effect between the implanted layer and the substrate seems to be present, and a bilayer model is applied to fit the measured properties. The fitted parameters follow the Meyer–Neldel rule. The role of the implantation tails in Si supersaturated with Ti is revealed in this work.Item Electrical characterization of gadolinium oxide deposited by high pressure sputtering with in situ plasma oxidation(Microelectronic Engineering, 2013) Pampillón. María Ángela; Feijoo. Pedro Carlos; San Andrés Serrano, EnriqueIn this work, we characterized gadolinium oxide films deposited on silicon by high pressure sputtering with a two-step process: first, we sputtered metallic gadolinium in an argon atmosphere and then, we performed an in situ plasma oxidation of the metallic layer previously deposited. By means of high resolution transmission electron microscopy, we can detect the oxidation degree of the metallic film. Under optimized deposition conditions, fully oxidized Gd2O3 films are obtained. In addition, the capacitance and conductance as a function of gate voltage of Pt gated metal–insulator–semiconductor capacitors confirm stable dielectric behavior of the fully oxidized films. The devices show low gate leakage currents (∼10−5 A/cm2 at 1 V for 2.2 nm of equivalent oxide thickness), low interface trap density and an almost negligible hysteresis and frequency dispersion.Item Effects of Gd2O3 Gate Dielectric on Proton-Irradiated AlGaN/GaN HEMTs(IEEE Electron Device Letters, 2017) Gao, Z.; Romero, M. F.; Redondo Cubero, A.; Pampillón, M. A.; San Andrés Serrano, Enrique; Calle, F.AlGaN/GaN high electron mobility transistors (HEMTs) and MOS-HEMTs using Gd2O3 as gate dielectric were irradiated with 2-MeV protons up to fluence of 1 x 10(15) cm(-2). Results showed that proton irradiation causes a strong degradation in the Schottky gate devices, featured by more than three orders of magnitude increase in reverse leakage current, a 30% decrease in maximum drain current, and the same percentage of increase in ON-resistance, respectively. Scanning transmission electron microscopy showed that radiation induced a diffusion of Ni into Au in the gate and void formation, degrading the transistors' characteristics. The Gd2O3 gate dielectric layer prevented this diffusion and void formation. MOS-HEMTs with Gd2O3 gate dielectric show 50% less decrease of performance under proton irradiation than Schottky gate HEMTs (conventional HEMTs). The trapping effects of Gd2O3 gate layer before and after irradiation are also discussed.Item High Pressure Sputtering of Mo targets in mixed Ar/O2/H2 atmospheres for hole selective contacts in photovoltaic cells(2023) Pérez Zenteno, Francisco José; San Andrés Serrano, Enrique; García Hemme, Eric; Torres, Ignacio; Barrio, Rocío; Caudevilla Gutiérrez, Daniel; Duarte Cano, Sebastián; García Hernansanz, Rodrigo; Olea Ariza, Javier; Pastor Pastor, David; Prado Millán, Álvaro DelWe have deposited thin films of MoO x using high-pressure sputtering (HPS) and Ar/O 2 /H 2 atmospheres aiming at the compositional and interface control. We found that H2 impacts plasma composition, which in turn produces a reduction of the oxygen content and a change in the refractive index of the films. However, the presence of hydrogen in the plasma atmosphere enhances interfacial SiO x regrowth, as FTIR shows. TEM measurements show that this regrowth is not critical for thin films. Also, increasing the hydrogen ratio produces a change from amorphous to an amorphous/polycrystalline mixture. Lifetime measurements show that these films are adequate for their integration into test HIT -like structures, but require more work to produce competitive iVoc values.Item Towards metal electrode interface scavenging of rare-earth scandates: A Sc2O3 and Gd2O3 study(Microelectronica engineering, 2011) Pampillón, María Ángela.; Feijoo, Pedro Carlos; San Andrés Serrano, Enrique; Toledano-Luque, María; Prado Millán, Álvaro Del; Blázquez, Antonio J.; Lucía Mulas, María LuisaAmorphous Gd2O3 and Sc2O3 thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiOx growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O2 atmosphere. For post-processing interfacial SiOx thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO2 interface thickness without severely compromising gate dielectric leakage.