Person:
Del Barrio García, Alberto Antonio

First Name

Alberto Antonio

Last Name

Del Barrio García

URI

https://hdl.handle.net/20.500.14352/78720

Affiliation

Universidad Complutense de Madrid

Faculty / Institute

Informática

Department

Arquitectura de Computadores y Automática

Area

Arquitectura y Tecnología de Computadores

Identifiers

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Now showing 1 - 10 of 19

HUB meets posit: arithmetic units implementation
(IEEE Transactions on Circuits and Systems II: Express Briefs, 2024) Murillo Montero, Raúl; Hormigo, Javier; Del Barrio García, Alberto Antonio; Botella Juan, Guillermo
The posit (TM) format was introduced in 2017 as an alternative to replacing the widespread IEEE 754. Posit arithmetic provides reproducible results across platforms and possesses tapered accuracy, among other improvements. Nevertheless, despite the advantages provided by such a format, their functional units are not as competitive as the IEEE 754 ones yet. The HUB approach was presented in 2016 to reduce the hardware cost of floating-point units. In this brief, we present HUB posit, a new format to mitigate the hardware overhead of posit units. Results show that it is possible to reach up to 15% and 12% in terms of area-delay product for adders and multipliers, respectively, while maintaining a similar level of accuracy. In addition, synthesis results show that HUB posit units are able to reach higher frequencies than conventional ones.
Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing
(IEEE Transactions on Computers, 2024) Mallasén Quintana, David; Del Barrio García, Alberto Antonio; Prieto Matías, Manuel
The accuracy requirements in many scientific computing workloads result in the use of double-precision floating-point arithmetic in the execution kernels. Nevertheless, emerging real-number representations, such as posit arithmetic, show promise in delivering even higher accuracy in such computations. In this work, we explore the native use of 64-bit posits in a series of numerical benchmarks and compare their timing performance, accuracy and hardware cost to IEEE 754 doubles. In addition, we also study the conjugate gradient method for numerically solving systems of linear equations in real-world applications. For this, we extend the PERCIVAL RISC-V core and the Xposit custom RISC-V extension with posit64 and quire operations. Results show that posit64 can obtain up to 4 orders of magnitude lower mean square error than doubles. This leads to a reduction in the number of iterations required for convergence in some iterative solvers. However, leveraging the quire accumulator register can limit the order of some operations such as matrix multiplications. Furthermore, detailed FPGA and ASIC synthesis results highlight the significant hardware cost of 64-bit posit arithmetic and quire. Despite this, the large accuracy improvements achieved with the same memory bandwidth suggest that posit arithmetic may provide a potential alternative representation for scientific computing.
Generating posit-based accelerators with high-level synthesis
(IEEE Transactions on Circuits and Systems I: Regular Papers, 2023) Murillo Montero, Raúl; Del Barrio García, Alberto Antonio; Botella Juan, Guillermo; Pilato, Christian
Recently, the posit number system has demonstrated a higher accuracy over standard floating-point arithmetic for many scientific applications. However, when it comes to implementing accelerators for these applications, the tool support for this arithmetic format is still missing, especially during the step. In this paper, we incorporate the posit data type into the high-level synthesis (HLS) design process, so that we can generate the implementation directly from a given behavioral specification, but using posit numbers instead of the classical floating-point notations. Our evaluations show that, even if posit-based circuits require more area than their floating-point counterparts, they offer higher accuracy when using the same bitwidth. For example, using posit arithmetic can reduce computation errors by about two orders of magnitude when compared to using standard floating-point numbers. Our approach also includes an alternative to mitigate the high overheads of the posits and broadening the potential use of this format. We also propose a hybrid scheme that uses posit numbers only in the private local memory, while the accelerator operates in the classic floating-point notation. This solution is useful when the designers want to optimize local memories and data transfers, but still use legacy high-level synthesis (HLS) tools that only support traditional floating-point notations.
Efectos de la Precisión Numérica en las Aplicaciones Cientı́ﬁcas
(2022) Murillo Montero, Raúl; Del Barrio García, Alberto Antonio; Botella Juan, Guillermo
A lo largo de las últimas décadas, han aparecido múltiples formatos como alternativas al estándar IEEE 754™ para la aritmética de coma flotante. El uso de formatos de precisión reducida, como bfloat16, o de nuevos sistemas aritméticos, como posit™, tiene un interés creciente no solo en el ámbito del aprendizaje automático, sino que también los algoritmos numéricos de propósito general pueden beneficiarse de esos formatos no estándar, reduciendo el tiempo de cálculo, el consumo de energía o los requisitos de memoria. Sin embargo, no siempre se dispone de hardware dedicado para los nuevos formatos aritméticos, y la simulación de diferentes precisiones numéricas es esencial para experimentar con esos formatos alternativos aún no implementados en hardware. En este trabajo, examinamos mediante emulación de software los efectos que tienen diferentes formatos aritméticos y precisiones numéricas en una amplia variedad de aplicaciones científicas. Demostramos los límites de la precisión numérica en cada aplicación, así como las ventajas de utilizar un formato aritmético u otro en cada situación. Los experimentos de este trabajo revelan que, con el mismo ancho de bits, la aritmética posit proporciona un error de hasta dos órdenes de magnitud menor que el formato de coma flotante.
Clúster de FPAAs para reconocimiento de imágenes mediante redes neuronales
(2022) García Moreno, Daniel; Del Barrio García, Alberto Antonio; Botella Juan, Guillermo
La computación analógica ha estado recuperando relevancia en los últimos años. Las Field-Programmable Analog Arrays (FPAAs) son dispositivos equivalentes a las Field-Programmable Gate Arrays, pero dentro del dominio analógico y de señal mixta. Con el objetivo de incrementar la cantidad de recursos analógicos, en este artículo se va a proponer el diseño y construcción de un clúster de 40 FPAAs. Como caso de uso, se ha implementado una red neuronal analógica de tipo feedforward 19-8-6-4 sobre el propio clúster. Con la ayuda de técnicas software basadas en la DCT, la red neuronal es capaz de clasificar imágenes de 28x28 píxeles del popular dataset MNIST. Los resultados obtenidos muestran que la red analógica puede obtener resultados similares a los de la red software de referencia y de mismas características.
Posit Arithmetic Units for Deep Neural Networks
(2021) Murillo Montero, Raúl; Del Barrio García, Alberto Antonio; Botella Juan, Guillermo
Posit™ arithmetic is a recent alternative format to the IEEE 754 standard for floating-point numbers that claims to provide compelling advantages over floats, including higher accuracy, larger dynamic range or bitwise compatibility across systems. In particular, this format is a suitable candidate to replace floating-point numbers in Deep Neural Networks (DNNs), an area of growing interest with a large computational cost. This work presents parameterized designs for multiple posit functional units, including addition, multiplication and multiply-accumulate operation, and integrate them as templates of the FloPoCo framework. Synthesis results show that the proposed arithmetic units significantly reduce the hardware requirements when compared with previous implementations. Finally, this work proposes the use of posit arithmetic for performing both DNN inference and training. Experiments on different datasets, including CIFAR-10, reveal that 16-bit posits can safely replace 32-bit floats for training, and that low-precision 8-bit posits can be used for DNN inference with negligible accuracy drop.
Project number: 18
Receptor Software de bajo coste e Interfaz Computerizada para el Estudio Práctico de las Comunicaciones Radioeléctricas
(2015) Del Barrio García, Alberto Antonio; Ayala Rodrigo, José Luis; Hermida Correa, Román
En este proyecto se ha desarrollado una plataforma de bajo coste de Software Defined Radio (SDR, Receptor Radio Software) que consta de una componente hardware y otra software, ambas libres. El uso de la interfaz software nos ha permitido modificar distintos parámetros de transmisión de la señal (filtrado de armónicos, frecuencia de muestreo, demodulador, etc.) y estudiar su impacto en la calidad de la señal mediante la síntesis audible a través del altavoz del PC.
Project number: 315
Enseñanza de coMputación cuántica Práctica pAra esTudiantes de Informática: Arquitectura y programación (EMPATIA)
(2021) Botella Juan, Guillermo; Del Barrio García, Alberto Antonio; Carrascal De Las Heras, Ginés; García Sánchez, Carlos; Murillo Montero, Raúl; García Moreno, Daniel; Fahmy Amin, Hesham Ahmed; Mas Aguilar, Juan; Roa Romero, Carlos; Sierra López, Angel
Plataforma de simulación y computación cuántica basada en hardware de bajo coste y tecnología de contenedores con posibilidad de ejecuciones en la nube. También metodología docente para la primera asignatura en UCM de Computación Cuántica práctica. "Arquitectura y Programación de Computadores Cuánticos" perteneciente a la Facultad de Informática.
Project number: 209
Tecnología paRa docenciA eN eScenarios de discapacidad basada en inteligencia artiFicial en tiempO-Real: Interprete de Signos Multicanal (TRANSFORM)
(2020) Botella Juan, Guillermo; Del Barrio García, Alberto Antonio; Clemente Barreira, Juan Antonio; López Alonso, José Manuel; Ezquerro Rodríguez, José Miguel; Piquer Otero, Andrés; Carrascal De Las Heras, Ginés; Roa Romero, Carlos; Mas Aguilar, Juan; Fahmy Amin, Hesham Ahmed; García Moreno, Daniel; Aguilera Calle, Iván; Sierra López, Angel; Cao García, Francisco Javier
Desarrollar un intérprete de signos en tiempo real mediante técnicas de aprendizaje profundo, aceleradores y procesado de video inteligente con objeto de desarrollar tiflotecnología barata, portable y accesible para toda la universidad.
Improving Circuit Performance with Multispeculative Additive Trees in High-Level Synthesis
(Microelectronics Journal, 2014) Del Barrio García, Alberto Antonio; Hermida Correa, Román; Ogrenci Memik, Seda; Mendías Cuadros, José Manuel; Molina Prego, María Del Carmen
The recent introduction of Variable Latency Functional Units (VLFUs) has broadened the design space of HighLevel Synthesis (HLS). Nevertheless their use is restricted to only few operators in the datapaths because the number of cases to control grows exponentially. In this work an instance of VLFUs is described, and based on its structure, the average latency of tree structures is improved. Multispeculative Functional Units (MSFUs) are arithmetic Functional Units that operate using several predictors for the carry signal. In spite of utilizing more than a predictor, none or only one additional very short cycle is enough for producing the correct result in the majority of the cases. In this paper our proposal takes advantage of multispeculation in order to increase the performance of tree structures with a negligible area penalty. By judiciously introducing these structures into computation trees, it will only be necessary to predict the carry signals in certain selected nodes, thus minimizing the total number of predictions and the number of operations that can potentially mispredict. Hence, the average latency will be diminished and thus performance will be increased. Our experiments show that it is possible to improve 26% execution time. Furthermore, our flow outperforms previous approaches with Speculative FUs.