Person:
Rodríguez Rodríguez, Roberto Alonso

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First Name
Roberto Alonso
Last Name
Rodríguez Rodríguez
URI
https://hdl.handle.net/20.500.14352/86791
Affiliation
Universidad Complutense de Madrid
Faculty / Institute
Informática
Department
Arquitectura de Computadores y Automática
Area
Arquitectura y Tecnología de Computadores
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2012 - 20183
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Now showing 1 - 3 of 3
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    Mecanismos de gestión de escrituras en sistemas con tecnologías de memoria no volátiles
    (2017) Rodríguez Rodríguez, Roberto Alonso; Castro Rodríguez, Fernando; Chaver Martínez, Daniel Ángel
    Since the beginning of computer systems, the memory subsystem has always been one of their essential components. However, the different pace of change between microprocessor and memory has become one of the greatest challenges that current designers have to address in order to develop more powerful computer systems. This problem, called memory gap, is further compounded by the limited scalability and the high energy consumption of conventional memory technologies (DRAM and SRAM), which has leaded to consider new non-volatile memory (NVM) technologies as potential candidates to replace them. Among NVMs, PCM and STT-RAM are currently postulated as the best alternatives. Although PCM and STT-RAM have significant advantages over DRAM and SRAM, they also suffer from some drawbacks that need to be mitigated before they can both be employed as memory technologies for the next computers generation. Notably, the slow and energy-hungry write operations on both technologies, and the limited endurance of PCM cells, which become unchangeable after performing a relatively reduced amount of writes on them, are the main constraints of PCM and STT-RAM technologies. This thesis presents two proposals aimed to efficiently manage the write operations on this kind of memories...
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    Evaluación y optimización de políticas de reemplazo caché en entornos PCM
    (2012) Rodríguez Rodríguez, Roberto Alonso; Piñuel Moreno, Luis; Castro Rodríguez, Fernando
    El diferente ritmo de evolución entre el microprocesador y la memoria principal constituye uno de los principales retos que los diseñadores deben afrontar para desarrollar computadores más potentes. A este problema, llamado brecha de memoria, se suma el hecho de que la capacidad de escalado de la tecnología DRAM es ya muy limitada actualmente, lo que conlleva que se consideren nuevas tecnologías de memoria como posibles candidatas a reemplazar a las convencionales DRAM. A día de hoy PCM se postula como la mejor alternativa para ello. PCM presenta importantes ventajas respecto a DRAM, pero también algunas debilidades que deben ser mitigadas antes de que PCM pueda ser empleada como tecnología de memoria principal. En particular, la vida útil de este tipo de memorias (limitada por el número de ciclos de escritura que se pueden realizar sobre cada celda) es uno de los principales inconvenientes de esta tecnología. En este trabajo se presenta un análisis del comportamiento, en cuanto a número de escrituras sobre memoria principal se refiere, de las políticas convencionales de reemplazo aplicadas a la caché; asimismo, se detallan nuevas propuestas de políticas orientadas a reducir el número de escrituras a memoria principal y de esta forma, sin degradar significativamente el rendimiento del sistema, aumentar la vida útil de la memoria cuando ésta se desarrolla usando la tecnología PCM. [Abstract] The different evolution rate between the microprocessor and the main memory is one of the greatest challenges that current designers face in order to develop more powerful computer systems. In addition to this problem, called memory gap, it is the fact that the scalability of the DRAM technology is very limited currently, leading to consider new memory technologies as possible candidates for the replacement of conventional DRAM. PCM is currently postulated as the best alternative for it. PCM has significant advantages over DRAM, but also some drawbacks that need to be mitigated before PCM can be used as main memory technology for the next computers generation. In particular, the endurance of this memory (the life time limited by the number of write cycles that can be performed on each cell) is one of the main drawbacks of this technology. This work presents a behavior analysis, in terms of number of writings on main memory, of conventional cache replacement policies. New proposals aimed at reducing the number of writes to main memory are exposed thought for increase the life time of the memory when it is developed using PCM technology, without significantly degrading the system performance.
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    Reuse detector: improving the management of STT-RAM SLLCs
    (The Computer Journal, 2018) Rodríguez Rodríguez, Roberto Alonso; Díaz, Javier; Castro Rodríguez, Fernando; Ibáñez, Pablo; Chaver Martínez, Daniel Ángel; Viñals, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel Moreno, Luis; Monreal, Teresa; Llabería, José María
    Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime contender due to its better energy efficiency, smaller die footprint and higher scalability. However, STT-RAM also exhibits some drawbacks, like slow and energy-hungry write operations that need to be mitigated before it can be used in SLLCs for the next generation of computers. In this work, we address these shortcomings by leveraging a new management mechanism for STT-RAM SLLCs. This approach is based on the previous observation that although the stream of references arriving at the SLLC of a Chip MultiProcessor (CMP) exhibits limited temporal locality, it does exhibit reuse locality, i.e. those blocks referenced several times manifest high probability of forthcoming reuse. As such, conventional STT-RAM SLLC management mechanisms, mainly focused on exploiting temporal locality, result in low efficient behavior. In this paper, we employ a cache management mechanism that selects the contents of the SLLC aimed to exploit reuse locality instead of temporal locality. Specifically, our proposal consists in the inclusion of a Reuse Detector (RD) between private cache levels and the STT-RAM SLLC. Its mission is to detect blocks that do not exhibit reuse, in order to avoid their insertion in the SLLC, hence reducing the number of write operations and the energy consumption in the STT-RAM. Our evaluation, using multiprogrammed workloads in quad-core, eight-core and 16-core systems, reveals that our scheme reports on average, energy reductions in the SLLC in the range of 37–30%, additional energy savings in the main memory in the range of 6–8% and performance improvements of 3% (quadcore), 7% (eight-core) and 14% (16-core) compared with an STT-RAM SLLC baseline where no RD is employed. More importantly, our approach outperforms DASCA, the state-of-the-art STT-RAM SLLC management, reporting —depending on the specific scenario and the kind of applications used— SLLC energy savings in the range of 4–11% higher than those of DASCA, delivering higher performance in the range of 1.5–14% and additional improvements in DRAM energy consumption in the range of 2–9% higher than DASCA.