Clemente Barreira, Juan Antonio

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First Name
Juan Antonio
Last Name
Clemente Barreira
Universidad Complutense de Madrid
Faculty / Institute
Arquitectura de Computadores y Automática
Arquitectura y Tecnología de Computadores
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Now showing 1 - 10 of 46
  • Publication
    Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems
    (IEEE, 2014-06) Clemente Barreira, Juan Antonio; Pérez Ramo, Elena; Resano, Javier; Mozos Muñoz, Daniel; Catthoor, Francky
    In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can introduce important overheads, both in terms of energy consumption and time, especially when configurations are fetched from an external memory. In order to address this problem, this article presents a configuration memory hierarchy including two on-chip memory modules with different access time and energy consumption features. In addition, we have developed two configuration mapping algorithms that take advantage of these memories to reduce the system energy consumption, while increasing its performance. The first algorithm has been optimized for systems with reduced dynamic behavior, hence it optimizes the system for each given set of tasks. The second algorithm targets dynamic systems where the active tasks change unpredictably. Thus, its objective is also to decrease the pressure on the on-chip memories to reduce capacity conflicts. The presented results will demonstrate that, with the proper management, our configuration memory hierarchy leads to an energy consumption reduction up to 81% with respect to fetching the configurations from the external memory, while keeping the system performance very close to the ideal upperbound one.
  • Publication
    Diseño y desarrollo de una placa de periféricos no convencionales para incentivar el aprendizaje autónomo sobre sistemas empotrados basados en FPGA y SoC ARM
    (2015-02-11) Fabero Jiménez, Juan Carlos; Mendías Cuadros, José Manuel; Mecha López, Hortensia; González Calvo, Carlos; Clemente Barreira, Juan Antonio
    Se plantea la adaptación y ampliación de la placa de periféricos desarrollada el curso anterior para su uso en otras asignaturas impartidas en nuestra Facultad, como son "Sistemas Empotrados Distribuidos" y "Programación de Sistemas y Dispositivos". En estas nuevas asignaturas se adopta el uso de microcontroladores basados en arquitectura ARM, por lo que se hace necesaria una adaptación de los controladores para poder emplear los periféricos que incorpora la placa. Asimismo, se ha planeado la ampliación de la placa de expansión para que incorpore, de manera integrada, los sensores analógicos y el motor paso a paso, así como nuevos dispositivos (detector de proximidad por ultrasonidos, por ejemplo) y otros controlados mediante el bus I2C, actualmente muy utilizado en la industria. Esta placa expandida permitirá generar un entorno adecuado para la programación de los distintos dispositivos de entrada/salida que pueden formar parte de un sistema empotrado, como los sensores y actuadores antes mencionados que, al ser dispositivos no convencionales, atraerán de manera especial la curiosidad del alumno.
  • Publication
    A Task-Graph Execution Manager for Reconfigurable Multi-tasking Systems
    (Elsevier, 2010-03) Clemente Barreira, Juan Antonio; González Calvo, Carlos; Resano, Javier; Mozos Muñoz, Daniel
    Reconfigurable hardware can be used to build multi tasking systems that dynamically adapt themselves to the requirements of the running applications. This is especially useful in embedded systems, since the available resources are very limited and the reconfigurable hardware can be reused for different applications. In these systems computations are frequently represented as task graphs that are executed taking into account their internal dependencies and the task schedule. The management of the task graph execution is critical for the system performance. In this regard, we have developed two dif erent versions, a software module and a hardware architecture, of a generic task-graph execution manager for reconfigurable multi-tasking systems. The second version reduces the run-time management overheads by almost two orders of magnitude. Hence it is especially suitable for systems with exigent timing constraints. Both versions include specific support to optimize the reconfiguration process.
  • Publication
    Single Event Upsets under 14-MeV Neutrons in a 28-nm SRAM-based FPGA in Static Mode
    (IEEE-Inst Electrical Electronics Engineers Inc, 2020) Fabero Jiménez, Juan Carlos; Mecha López, Hortensia; Franco Peláez, Francisco Javier; Clemente Barreira, Juan Antonio; Korkian, Golnaz; Rey, Solenne; Cheymol, Benjamin; Baylac, Maud; Hubert, Guillaume; Velazco, Raoul
    A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.
  • Publication
    Inherent Uncertainty in the Determination of Multiple Event Cross Sections in Radiation Tests
    (IEEE-Inst Electrical Electronics Engineers Inc, 2020) Franco Peláez, Francisco Javier; Clemente Barreira, Juan Antonio; Korkian, Golnaz; Fabero Jiménez, Juan Carlos; Mecha López, Hortensia; Velazco, Raoul
    In radiation tests on SRAMs or FPGAs, two or more independent bitflips can be misled with a multiple event if they accidentally occur in neighbor cells. In the past, different tests such as the ``birthday statistics'' have been proposed to estimate the accuracy of the experimental results. In this paper, simple formulae are proposed to determine the expected number of false 2-bit and 3-bit MCUs from the number of bitflips, memory size and the method used to search multiple events. These expressions are validated using Monte Carlo simulations and experimental data. Also, a technique is proposed to refine experimental data and thus partially removing possible false events. Finally, it is demonstrated that there is a physical limit to determine the cross section of memories with arbitrary accuracy from a single experiment.
  • Publication
    Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons
    (IEEE, 2016-08) Ramos, Pablo; Vargas Vallejo, Vanessa Carolina; Baylac, Maud; Villa, Francesca; Rey, Solenne; Clemente Barreira, Juan Antonio; Zergainoh, Nacer-Eddine; Méhaut, Jean-François
    The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used.
  • Publication
    Impact of High Particle Flux in Radiation Ground Tests with Protons
    (IEEE eXpress Conference Publishing, 2022-08-22) Rezaei, Mohammadreza; Martín Holgado, Pedro; Morilla García, Yolanda; Franco Peláez, Francisco Javier; Fabero Jiménez, Juan Carlos; Mecha López, Hortensia; Puchner, Helmut; Hubert, Guillaume; Clemente Barreira, Juan Antonio
    This abstract presents an experimental study of the impact of using a high flux in radiation ground tests on the measured cross-section of SRAMs. Experimental results obtained with 15 MeV protons will show that using a high particle flux makes the measured cross-section increase by almost 1 order of magnitude.
  • Publication
    SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles
    (Elsevier, 2023-12-10) Fabero Jiménez, Juan Carlos; Korkian, Golnaz; Franco, Francisco J.; Hubert, Guillaume; Mecha López, Hortensia; Letiche, Manon; Clemente Barreira, Juan Antonio
    This paper provides an experimental study of the single-event upset (SEU) susceptibility against thermal neutron radiation of a 28-nm bulk Commercial-Off-The-Shelf (COTS) Xilinx Artix-7 FPGA under different angles of incidence. Experimental results indicating SEUs on configuration RAM (CRAM) cells, Flip-Flops (FFs), and Block RAMs (BRAMs) are presented and discussed. Shapes of multiple events (ranging from 2 to 12-bit) are also analyzed, and their dependency on the incident angle of the particle beam against the device’s surface. Possible shapes of 128 and 384-bit multiple events are also investigated, revealing a trend to follow word lines. The results of the front incident angle are compared with 14.2-MeV neutrons, demonstrating a considerable difference in the device’s sensitivity against both irradiation sources. Finally, a modeling tool called MUSCA-SEP3 is used to predict the device’s sensitivity under the same environmental conditions. The obtained experimental results will show a good agreement with the predicted ones in a very accurate way.
  • Publication
    Impact of Dynamic Voltage Scaling on SEU Sensitivity of COTS Bulk SRAMs and A-LPSRAMs against Proton Radiation
    (IEEE, 2022-01-05) Rezaei, Mohammadreza; Hubert, Guillaume; Martín-Holgado, Pedro; Morilla, Yolanda; Fabero Jiménez, Juan Carlos; Mecha López, Hortensia; Franco Peláez, Francisco Javier; Clemente Barreira, Juan Antonio
    In the aerospace industry, commercial-off-the-shelf (COTS) static random access memories (SRAMs) are a cost-effective solution for obtaining high performance at the system level, which is difficult to obtain using space-qualified components. In addition, the usage of dynamic voltage scaling (DVS) is commonly used in space environments, where low power consumption is a critical issue. This article presents an analysis of the sensitivity against single-event upsets (SEUs) of various COTS bulk SRAMs and advanced low-power SRAMs (A-LPSRAMs) against proton radiation when using DVS to save power. Experimental results will show clear evidence that the sensitivity to SEUs increases when the power is lowered. Two sets of successive technologies (130-, 90-, and 65-nm bulk SRAMs, and 150- and 110-nm A-LPSRAMs) are evaluated against 15-MeV protons and compared with results of 14-MeV neutrons presented in a previous work. Experimental data are finally compared with analytical simulations obtained by using the multiscales single-event phenomena predictive platform (MUSCA-SEP3) Monte Carlo tool to predict the effect of DVS on the SEE sensitivity on more modern technologies in the ITRS/IRDS roadmap.
  • Publication
    A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
    (IEEE, 2011-07) Clemente Barreira, Juan Antonio; Resano, Javier; González Calvo, Carlos; Mozos Muñoz, Daniel
    New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on As-Soon-As-Possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.