High-throughput architecture for post-quantum DME cryptosystem
dc.contributor.author | Imaña Pascual, José Luis | |
dc.contributor.author | Luengo Velasco, Ignacio | |
dc.date.accessioned | 2023-06-16T15:26:40Z | |
dc.date.available | 2023-06-16T15:26:40Z | |
dc.date.issued | 2020-11 | |
dc.description | © 2020 Elsevier This work has been supported by the Spanish MINECO and CM under grants S2018/TCS-4423, TIN 2015-65277-R and RTI2018-093684-B-I00. | |
dc.description.abstract | Quantum computers have the potential to solve difficult mathematical problems efficiently, therefore meaning an important threat to Public-Key Cryptography (PKC) if large-scale quantum computers are ever built. The goal of Post-Quantum Cryptography (PQC) is to develop cryptosystems that are secure against both classical and quantum computers. DME is a new proposal of quantum-resistant PKC algorithm that was presented for NIST PQC Standardization competition in order to set the next-generation of cryptography standards. DME is a multivariate public key, signature and Key Encapsulation Mechanism (KEM) system based on a new construction of the central maps, that allows the polynomials of the public key to be of an arbitrary degree. In this paper, a high-throughput pipelined architecture of DME is presented and hardware implementations over Xilinx FPGAs have been performed. Experimental results show that the architecture here presented exhibits the lowest execution time and highest throughput when it is compared with other PQC multivariate implementations given in the literature. | |
dc.description.department | Sección Deptal. de Arquitectura de Computadores y Automática (Físicas) | |
dc.description.faculty | Fac. de Ciencias Físicas | |
dc.description.refereed | TRUE | |
dc.description.sponsorship | Ministerio de Ciencia e Innovación (MICINN)/FEDER | |
dc.description.sponsorship | Ministerio de Economía y Competitividad (MINECO) | |
dc.description.sponsorship | Comunidad de Madrid | |
dc.description.status | pub | |
dc.eprint.id | https://eprints.ucm.es/id/eprint/62793 | |
dc.identifier.doi | 10.1016/j.vlsi.2020.07.002 | |
dc.identifier.issn | 0167-9260 | |
dc.identifier.officialurl | http://dx.doi.org/10.1016/j.vlsi.2020.07.002 | |
dc.identifier.relatedurl | https://www.sciencedirect.com | |
dc.identifier.uri | https://hdl.handle.net/20.500.14352/6687 | |
dc.journal.title | Integration-the VLSI journal | |
dc.language.iso | eng | |
dc.page.final | 121 | |
dc.page.initial | 114 | |
dc.publisher | Elsevier | |
dc.relation.projectID | RTI2018-093684-B-I00 | |
dc.relation.projectID | TIN 2015-65277-R | |
dc.relation.projectID | CABAHLA-CM (S2018/TCS-4423) | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 España | |
dc.rights.accessRights | open access | |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/es/ | |
dc.subject.cdu | 004.8 | |
dc.subject.keyword | Signature | |
dc.subject.keyword | Hardware | |
dc.subject.keyword | Rainbow | |
dc.subject.keyword | Past-quantum cryptography | |
dc.subject.keyword | Multivariate public-key cryptosystem | |
dc.subject.keyword | DME | |
dc.subject.keyword | Finite field | |
dc.subject.keyword | Field-Programmable Gate Array (FPGA) | |
dc.subject.keyword | Pipelined | |
dc.subject.keyword | High-throughput | |
dc.subject.ucm | Inteligencia artificial (Informática) | |
dc.subject.unesco | 1203.04 Inteligencia Artificial | |
dc.title | High-throughput architecture for post-quantum DME cryptosystem | |
dc.type | journal article | |
dc.volume.number | 75 | |
dspace.entity.type | Publication | |
relation.isAuthorOfPublication | 1c42e591-4b3d-4cb4-919d-01813fa4cd36 | |
relation.isAuthorOfPublication | 2e3a1e05-10b8-4ea5-9fcc-b53bbb0168ce | |
relation.isAuthorOfPublication.latestForDiscovery | 1c42e591-4b3d-4cb4-919d-01813fa4cd36 |
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