Evaluation of the Intel Thread Director Technology on an Alder Lake processor

Abstract

Asymmetric multicore processors (AMPs) combine high-performance big cores with more energy-efficient small cores, all exposing a shared instruction-set architecture but different features, such as clock frequency or microarchitecture. In the last decade, most commercial AMP products have mainly targetted the embedded and mobile domains. Today, major hardware players are releasing new AMP-based products that aim to move beyond the mobile niche, towards the desktop/server segments. The Apple M1 SoC or the recent Intel Alder Lake processor family are clear examples of these new AMP systems. Despite their energy-efficiency benefits, AMPs pose significant challenges to the operating system scheduler. In this paper, we assess the effectiveness of the Thread Director (TD) technology, a set of hardware facillities - first introduced in Alder Lake processors - that provide the OS with hints on the performance and energy efficiency that a thread delivers when running on the various core types. The main focus of our analysis is to evaluate how effectively the OS can drive scheduling decisions with TD's performance hints. To this end, we incorporated support in Linux to conveniently access TD facillites from the OS kernel. Motivated by various TD's limitations identified with our analysis, we opted to build hardware-counter based prediction models (generated via machine-learning methods) to better aid the OS in making throughput-oriented and fairness-aware scheduling decisions. The effectiveness of both TD and the hardware-counter based models for performance prediction is evaluated both via offline monitoring, and also online, by utilizing our implementation of various asymmetry-aware schedulers in the Linux kernel.