Diseño y simulación de sistemas neuromórficos mediante computación analógica
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2025
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Abstract
Este trabajo presenta el diseño y verificación de un sistema neuromórfico mixto basado en el modelo de Izhikevich, empleando ́técnicas de verificación ́ formal y simulación electrónica. Se desarrolla un entorno simbólico en Python que permite representar circuitos hardware mediante restricciones lógicas, las cuales son verificadas automáticamente mediante el resolutor SMT Z3. Asimismo, se implementa un banco de pruebas hardware en Siemens PartQuest, que recorre de forma determinista el espacio de entradas para garantizar el cumplimiento funcional. La propuesta sigue los principios establecidos por los estándares DO-254 y DO-333, integrando la trazabilidad normativa, la validación funcional y la comprobación lógica en un mismo entorno. El trabajo demuestra la viabilidad de una metodología combinada basada en modelado simbólico, verificación automatizada y simulación exhaustiva
de hardware.
This work presents the design and verification of a mixed neuromorphic system based on the Izhikevich model, using formal verification techniques and electronic simulation. A symbolic environment in Python is developed, allowing hardware circuits to be represented through logical constraints, which are automatically verified using the Z3 SMT solver. Additionally, a hardware testbench is implemented in Siemens PartQuest, deterministically exploring the input space to ensure functional compliance. The proposed approach follows the principles of the DO-254 and DO-333 standards, integrating regulatory traceability, functional validation, and logical verification within a unified environment. The project demonstrates the feasibility of a combined methodology based on symbolic modeling, automated verification, and exhaustive hardware simulation.
This work presents the design and verification of a mixed neuromorphic system based on the Izhikevich model, using formal verification techniques and electronic simulation. A symbolic environment in Python is developed, allowing hardware circuits to be represented through logical constraints, which are automatically verified using the Z3 SMT solver. Additionally, a hardware testbench is implemented in Siemens PartQuest, deterministically exploring the input space to ensure functional compliance. The proposed approach follows the principles of the DO-254 and DO-333 standards, integrating regulatory traceability, functional validation, and logical verification within a unified environment. The project demonstrates the feasibility of a combined methodology based on symbolic modeling, automated verification, and exhaustive hardware simulation.
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Trabajo de Fin de Grado en Ingeniería Informática, Facultad Informática UCM, Dpto. de Arquitectura de Computadores y Automática, Curso 2024/2025













