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A Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs

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dc.conference.date23-27 Sept. 2013
dc.conference.titleRadiation and Its Effects on Components and Systems (RADECS), 2013 14th European Conference on
dc.contributor.authorSerrano, Felipe
dc.contributor.authorClemente Barreira, Juan Antonio
dc.contributor.authorMecha López, Hortensia
dc.date.accessioned2023-06-19T16:04:40Z
dc.date.available2023-06-19T16:04:40Z
dc.date.issued2014-10-30
dc.description© © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractIn this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.
dc.description.departmentDepto. de Arquitectura de Computadores y Automática
dc.description.facultyFac. de Informática
dc.description.refereedTRUE
dc.description.sponsorshipMinisterio de Economía y Competitividad (MINECO)
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/39514
dc.identifier.officialurlhttp://dx.doi.org/10.1109/RADECS.2013.6937459
dc.identifier.urihttps://hdl.handle.net/20.500.14352/36155
dc.language.isospa
dc.relation.projectIDAYA2009-13300-C03-02
dc.relation.projectIDTIN2009-09806
dc.rights.accessRightsopen access
dc.subject.cdu004.312
dc.subject.keywordField programmable gate arrays
dc.subject.keywordDigital signal processing
dc.subject.keywordCircuit faults
dc.subject.keywordRobustness
dc.subject.keywordDigital circuits
dc.subject.keywordSingle event upsets
dc.subject.keywordEmulation
dc.subject.ucmHardware
dc.titleA Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs
dc.typeconference paper
dspace.entity.typePublication
relation.isAuthorOfPublication919b239d-a500-4adb-aacf-00206a2c1512
relation.isAuthorOfPublication2363ed06-f92b-4c10-bd9a-87ac2fcce006
relation.isAuthorOfPublication.latestForDiscovery919b239d-a500-4adb-aacf-00206a2c1512

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