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Formal correctness of a passive testing approach for timed systems

dc.book.titleICSTW 2009: IEEE International Conference on Software Testing, Verification, and Validation Workshops
dc.contributor.authorGarcía Merayo, María De Las Mercedes
dc.contributor.authorAndrés Sánchez, César
dc.contributor.authorNúñez García, Manuel
dc.date.accessioned2023-06-20T05:44:11Z
dc.date.available2023-06-20T05:44:11Z
dc.date.issued2009-04
dc.descriptionInternational Conference on Software Testing, Verification, and Validation Workshops. APR 01-04, 2009. Denver, CO.
dc.description.abstractIn this paper we extend our previous work on passive testing of timed systems to establish a formal criterion to determine correctness of an implementation under test. In our framework, an invariant expresses the fact that if the implementation under test performs a given sequence of actions, then it must exhibit a behavior in a lapse of time reflected in the invariant. In a previous paper we gave an algorithm to establish the correctness of an invariant with respect to a specification. In this paper we continue the work by providing an algorithm to check the correctness of a log, recorded form the implementation under test, with respect to an invariant. We show the soundness of our method by relating it to an implementation relation. In addition to the theoretical framework we have developed a tool, called PASTE, that facilitates the automation of our passive testing approach.
dc.description.departmentSección Deptal. de Sistemas Informáticos y Computación
dc.description.facultyFac. de Ciencias Matemáticas
dc.description.refereedTRUE
dc.description.sponsorshipMEC
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/15629
dc.identifier.doi10.1109/ICSTW.2009.34
dc.identifier.isbn978-0-7695-3671-2
dc.identifier.officialurlhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4976372
dc.identifier.relatedurlhttp://www.ieee.org/
dc.identifier.urihttps://hdl.handle.net/20.500.14352/45319
dc.language.isoeng
dc.page.total76
dc.publication.placeLOS ALAMITOS
dc.publisherIEEE Comp Soc
dc.relation.projectIDTIN2006-15578-C02-01
dc.rights.accessRightsopen access
dc.subject.cdu519.8
dc.subject.keywordFinite-state machines
dc.subject.ucmMatemáticas (Matemáticas)
dc.subject.ucmInvestigación operativa (Matemáticas)
dc.subject.unesco12 Matemáticas
dc.subject.unesco1207 Investigación Operativa
dc.titleFormal correctness of a passive testing approach for timed systems
dc.typebook part
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