A power-efficient and scalable load-store queue design

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dc.book.titleIntegrated circuit and system design: power and timing modeling, optimization and simulation
dc.contributor.authorCastro, F.
dc.contributor.authorChaver Martínez, Daniel Ángel
dc.contributor.authorPiñuel Moreno, Luis
dc.contributor.authorPrieto Matías, Manuel
dc.contributor.authorHuang, M. C.
dc.contributor.authorTirado Fernández, Francisco
dc.date.accessioned2023-06-20T13:41:50Z
dc.date.available2023-06-20T13:41:50Z
dc.date.issued2005
dc.description© Springer-Verlag Berlin Heidelberg 2005. We want to thank Simha Sethumadhavan for his helpful and thorough comments. International Workshop on Power and Timing Modeling, Optimization and Simulation (15th. sep 21-23, 2005.Lovaina, Belgica).
dc.description.abstractThe load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.
dc.description.departmentSección Deptal. de Arquitectura de Computadores y Automática (Físicas)
dc.description.facultyFac. de Ciencias Físicas
dc.description.refereedTRUE
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/29749
dc.identifier.citation1. R. E. Kessler. The Alpha 21264 Microprocessor. Technical Report, Compaq Computer Corporation, 1999. 2. B. Calder and G. Reinman. A Comparative Survey of Load Speculation Architectures. Journal of Instruction-Level Parallelism, May-2000. 3. C. Nairy and D. Soltis. Itanium-2 Processor Microarchitecture. IEEE-Micro, 23(2):44-55, March/April, 2003. 4. J. M. Tendler, J. S. Dodson, J. S. Fields Jr., H. Le and B. Sinharoy. Power-4 System Microarchitecture. IBM Journal of Research and Development, 46(1):5-26, 2002. 5. S. Sethumadhavan, R. Desikan, D. Burger, Charles R. Moore, Stephen W. Keckler. Scalable Hardware Memory Disambiguation for High ILP Processors. Proceedings of MICRO-36, December-2003. 6. T. Austin, E. Larson, and D. Ernst. SimpleScalar: An Infrastructure for Computer System Modeling. Computer, vol. 35, no. 2, Feb 2002. 7. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. 28-ISCA, Göteborg, Sweden. July, 2001. 8. T. Sherwood, E. Perelman, G. Hamerly, B. Calder. Automatically charecterizing large scale program behavior . Proceedings of ASPLOS-2002, October-2002. 9. S. Sethumadhavan, R. Desikan, D. Burger, Charles R. Moore, Stephen W. Keckler. Scalable Hardware Memory Disambiguation for High ILP Processors. IEEE-Micro, Vol. 24, Issue 6:118-127, November/December, 2004. 10. I. Park, C. Liang Ooi, T. N. Vijaykumar. Reducing design complexity of the load-store queue. Proceedings of MICRO-36, December-2003. 11. H. W. Cain and M. H. Lipasti. Memory Ordering: A Value-Based Approach. Proceedings of ISCA-31, June-2004. 12. A. Roth. A high-bandwidth load-store unit for single- and multi- threaded processors. Technical Report, University of Pennsylvania, 2004. 13. L. Baugh and C. Zilles. Decomposing the Load-Store Queue by Function for Power Reduction and Scalability. Proceedings of PAC Conference, October-2004.
dc.identifier.isbn3-540-29013-3
dc.identifier.officialurlhttp://link.springer.com/chapter/10.1007/11556930_1
dc.identifier.relatedurlhttp://link.springer.com
dc.identifier.relatedurlhttp://www.ece.rochester.edu/~mihuang/PAPERS/patmos05.pdf
dc.identifier.urihttps://hdl.handle.net/20.500.14352/53421
dc.language.isoeng
dc.page.final9
dc.page.initial1
dc.publisherSpringer-Verlag Berlin
dc.rights.accessRightsopen access
dc.subject.cdu004
dc.subject.keywordComputer science
dc.subject.keywordhardware & architecture
dc.subject.keywordtheory & methods
dc.subject.keywordEngineering
dc.subject.keywordelectrical & electronic
dc.subject.ucmInformática (Informática)
dc.subject.ucmProgramación de ordenadores (Informática)
dc.subject.unesco1203.17 Informática
dc.subject.unesco1203.23 Lenguajes de Programación
dc.titleA power-efficient and scalable load-store queue design
dc.typebook part
dc.volume.number3728
dspace.entity.typePublication
relation.isAuthorOfPublication6b8b1488-47cc-441e-921b-c1e8042d627c
relation.isAuthorOfPublication2ce782af-0e05-45eb-b58a-d2efffec6785
relation.isAuthorOfPublication5d3f6717-1495-4217-853c-8c9c75d56620
relation.isAuthorOfPublication.latestForDiscovery6b8b1488-47cc-441e-921b-c1e8042d627c
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