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Deadlock-Guided Testing

dc.contributor.authorIsabel Márquez, Miguel
dc.contributor.authorGómez-Zamalloa Gil, Miguel
dc.contributor.editorPorfirio Tramontana
dc.date.accessioned2024-02-05T15:27:11Z
dc.date.available2024-02-05T15:27:11Z
dc.date.issued2021-03-21
dc.description.abstractStatic deadlock analyses might be able to verify the absence of deadlock. However, they are usually not able to detect its presence. Moreover, when a potential deadlock is detected, they provide little (and often no) information that can help the user in finding the source of the anomalous behaviour. This paper proposes a testing methodology that combines static analysis and symbolic execution for effective deadlock detection in asynchronous programs. When the program features a deadlock, our testing methodology provides an effective technique to catch deadlock traces. While if the program does not have deadlock, but the static deadlock analysis inaccurately spotted it, our approach is able to prove deadlock freedom (up to the limit of the performed symbolic exploration).
dc.description.departmentDepto. de Sistemas Informáticos y Computación
dc.description.facultyFac. de Informática
dc.description.refereedTRUE
dc.description.sponsorshipMinisterio de Ciencia, Innovación y Universidades (RTI2018-094403-B-C31)
dc.description.sponsorshipComunidad de Madrid (S2018/TCS-4314 y S2018/TCS-4339)
dc.description.sponsorshipMinsterio de Educación Cultura y Deporte (FPU15/04313)
dc.description.statuspub
dc.identifier.citationM. Gómez-Zamalloa and M. Isabel, "Deadlock-Guided Testing," in IEEE Access, vol. 9, pp. 46033-46048, 2021
dc.identifier.doi10.1109/ACCESS.2021.3065421
dc.identifier.essn2169-3536
dc.identifier.officialurlhttps://ieeexplore.ieee.org/document/9374914
dc.identifier.urihttps://hdl.handle.net/20.500.14352/99066
dc.journal.titleIEEE Access
dc.language.isoeng
dc.page.final46048
dc.page.initial46033
dc.publisherIEEE
dc.relation.projectIDinfo:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/RTI2018-094403-B-C31/ES/RAZONAMIENTO FORMAL PARA TECNOLOGIAS FACILITADORAS Y EMERGENTES/
dc.rightsAttribution-NonCommercial-ShareAlike 4.0 Internationalen
dc.rights.accessRightsopen access
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/
dc.subject.keywordDeadlock analysis
dc.subject.keywordDeadlock detection
dc.subject.keywordSymbolic execution
dc.subject.keywordTesting
dc.subject.keywordTest case generation
dc.subject.keywordVerification
dc.subject.ucmLenguajes de programación
dc.subject.unesco33 Ciencias Tecnológicas
dc.titleDeadlock-Guided Testing
dc.typejournal article
dc.type.hasVersionVoR
dc.volume.number9
dspace.entity.typePublication
relation.isAuthorOfPublication06ba5ba7-fae5-4f98-99b7-3830106dee88
relation.isAuthorOfPublication6eef4c69-fd36-4274-b9c2-e93105ad2268
relation.isAuthorOfPublication.latestForDiscovery6eef4c69-fd36-4274-b9c2-e93105ad2268

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