A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs

dc.conference.date17-20 Nov 2019
dc.conference.placeAbu Dhabi
dc.conference.titleInternational Conference on Computer Design (ICCD) 2019
dc.contributor.authorEvenblij, Timmon
dc.contributor.authorKomalan, Manu Perumkunnil
dc.contributor.authorCatthoor, Franky
dc.contributor.authorSakhare, Sushil
dc.contributor.authorDebacker, Peter
dc.contributor.authorKar, Gouri
dc.contributor.authorFurnemont, Arnaud
dc.contributor.authorBueno Mora, Nicolás
dc.contributor.authorGómez Pérez, José Ignacio
dc.contributor.authorTenllado Van Der Reijden, Christian Tomás
dc.contributor.editorIEEE
dc.date.accessioned2024-02-12T10:56:10Z
dc.date.available2024-02-12T10:56:10Z
dc.date.issued2019-11-17
dc.description.abstractSpin Transfer Torque Magnetic RAM (STT-MRAM) is being extensively considered as a promising replacement for Last Level Caches (LLC), due to its high density, low leakage and non-volatility. However, writes to STT-MRAM are energy intensive and have a high latency. While the high dynamic energy consumption during writes can be compensated by the low static energy consumption, the high latency results in performance degradation. This work shows that in contrast to SRAM-based LLCs, the performance degradation for STT-MRAM is primarily due to bank contention, when trying to satisfy a read request while the bank is being written. We holistically explore the effects of cache banking and cache contention on energy and performance in the LLC of mobile multicore systems, with in-order cores or with out-of-order cores. The detail of the analysis is enabled by highly accurate cache models, based on a 28nm SRAM industry compiler, and an in-house developed STT-MRAM compiler, which generates full STT-MRAM macro designs with silicon-validated MTJ stack and complete parasitic extraction at the 28nm node. Our results show that there is a clear difference in the energy-performance optimal banking configuration between STT-MRAM caches and SRAM caches. These low contention STT-MRAM cache designs with the optimal number of banks save at least 60% cache energy while losing at most single digit percentages in system performance compared to SRAM cache designs. This show an increased potential of using STT-MRAM as a replacement for SRAM in an LLC.
dc.description.departmentDepto. de Arquitectura de Computadores y Automática
dc.description.facultyFac. de Informática
dc.description.refereedTRUE
dc.description.sponsorshipEU (FEDER)
dc.description.sponsorshipMINECO
dc.description.sponsorshipComunidad de Madrid
dc.description.statuspub
dc.identifier.citationT. Evenblij et al., "A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs," 2019 IEEE 37th International Conference on Computer Design (ICCD), Abu Dhabi, United Arab Emirates, 2019, pp. 255-263, doi: 10.1109/ICCD46524.2019.00039.
dc.identifier.doi10.1109/ICCD46524.2019.00039
dc.identifier.officialurlhttps://ieeexplore.ieee.org/document/8988649/authors
dc.identifier.urihttps://hdl.handle.net/20.500.14352/101213
dc.language.isoeng
dc.page.final263
dc.page.initial255
dc.relation.projectIDTIN2015-65277-R
dc.relation.projectIDRTI2018-093684-B-I00
dc.relation.projectIDS2018/TCS-4423
dc.rights.accessRightsopen access
dc.subject.keywordSTT-MRAM;Cache bank;Performance;Energy;Contention
dc.subject.ucmHardware
dc.subject.unesco3304.06 Arquitectura de Ordenadores
dc.titleA Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs
dc.typeconference paper
dc.type.hasVersionAO
dspace.entity.typePublication
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relation.isAuthorOfPublication.latestForDiscoveryc6b7d4bb-48ca-41a4-b22a-3fd1d5a1a1e9
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