A real-time FPGA implementation of the CCSDS 123.0-B-2 standard

Abstract

Hyperspectral images are a useful remote sensing tool which often reach hundreds of megabytes in size. The CCSDS 123.0-B-2 is a recent algorithm that achieves lossless and nearlossless compression of hyperspectral images by introducing a configurable maximum error over its predecessor CCSDS 123.0- B-1. In this paper, an FPGA implementation of the revised standard that works in real-time is presented. We have developed an extremely pipelined and fast core in VHDL, that is able to process a sample per cycle at over 250MHz, working 8 times faster than real-time for the AVIRIS-NG sensor. New dependencies in the revised standard are avoided by using a novel sample ordering called Frame Interleaved by Diagonal. The predictor stage has been designed to work in this order, and two reorder buffers encapsulate it to be Band Interleaved by Pixel compliant. Predictor data is encoded using a novel FPGA implementation of the CCSDS 123.0-B-2 hybrid coder. The modules are tested and verified on a Virtex-7 VC709 board. For medium (256 bands × 4096 frames × 512 samples) and large (512×4096×1024) images, the core occupies respectively 14% and 50% of a XQRKU060 FPGA.