A methodology for automatic insertion of selective TMR in digital circuits affected by SEUs

Abstract

In this paper, a methodology to perform automatic selective TMR insertion on digital circuits is presented, having as a constraint the required reliability level. Such reliability is guaranteed while reducing the area compared to TMR. In addition, a performance enhancement is proposed in order to guarantee a computation time feasible for this automatic selective TMR insertion methodology. It focuses on the choice of a starting point close enough to an optimal solution. The method consists in the analysis of the topological features of the target circuit which will help the optimization engine to identify those flip-flops more susceptible to be tripled depending on the showed sensitivity to SEUs.