Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices

Simple item page
dc.contributor.authorKomalan, Manu
dc.contributor.authorGupta, Mohit
dc.contributor.authorCatthoor, Francky
dc.contributor.authorGómez Pérez, José Ignacio
dc.contributor.authorMarinelli, Tommaso
dc.contributor.authorTenllado Van Der Reijden, Christian Tomás
dc.date.accessioned2024-01-30T12:52:16Z
dc.date.available2024-01-30T12:52:16Z
dc.date.issued2022-01-20
dc.description.abstractAs the technology scaling advances, limitations of traditional memories in terms of density and energy become more evident. Modern caches occupy a large part of a CPU physical size and high static leakage poses a limit to the overall efficiency of the systems, including IoT/edge devices. Several alternatives to CMOS SRAM memories have been studied during the past few decades, some of which already represent a viable replacement for different levels of the cache hierarchy. One of the most promising technologies is the spin-transfer torque magnetic RAM (STT-MRAM), due to its small basic cell design, almost absent static current and nonvolatility as an added value. However, nothing comes for free, and designers will have to deal with other limitations, such as the higher latencies and dynamic energy consumption for write operations compared to reads. The goal of this work is to explore several microarchitectural parameters that may overcome some of those drawbacks when using STT-MRAM as last-level cache (LLC) in embedded devices. Such parameters include: number of cache banks, number of miss status handling registers (MSHRs) and write buffer entries, presence of hardware prefetchers. We show that an effective tuning of those parameters may virtually remove any performance loss while saving more than 60% of the LLC energy on average. The analysis is then extended comparing the energy results from calibrated technology models with data obtained with freely available tools, highlighting the importance of using accurate models for architectural exploration.
dc.description.departmentDepto. de Arquitectura de Computadores y Automática
dc.description.facultyFac. de Informática
dc.description.refereedTRUE
dc.description.statuspub
dc.identifier.doi10.1145/3490391
dc.identifier.issn1539-9087
dc.identifier.officialurlhttps://doi.org/10.1145/3490391
dc.identifier.urihttps://hdl.handle.net/20.500.14352/96520
dc.issue.number1
dc.journal.titleACM Transactions on Embedded Computing Systems (TECS)
dc.language.isoeng
dc.publisherAssociation for Computing Machinery
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internationalen
dc.rights.accessRightsopen access
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.subject.keywordEnergy efficiency, gem5, last-level cache, nvsim, spec cpu2017, stt-mram
dc.subject.ucmHardware
dc.subject.unesco3304 Tecnología de Los Ordenadores
dc.titleMicroarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices
dc.typejournal article
dc.type.hasVersionAM
dc.volume.number21
dspace.entity.typePublication
relation.isAuthorOfPublicatione83f8db2-0fb6-4141-8ec5-d20d09ce194d
relation.isAuthorOfPublication32a60d4c-7033-48ca-8d40-47f955d42217
relation.isAuthorOfPublicationd47f11bf-2134-459b-bcf7-6e1efa4aa8b6
relation.isAuthorOfPublication.latestForDiscoverye83f8db2-0fb6-4141-8ec5-d20d09ce194d
Download
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
3490391.pdf
Size:
1.18 MB
Format:
Adobe Portable Document Format
downoload Download
Collections
Artículos