Publication:
A machine learning-based framework for throughput estimation of time-varying applications in multi-core servers

dc.book.title2019 IFIP/IEEE 27th International conference on very large scale integration (VLSI-SOC)
dc.contributor.authorIranfar, Arman
dc.contributor.authorSouza, Wellington Silva de
dc.contributor.authorZapater, Marina
dc.contributor.authorOlcoz Herrero, Katzalin
dc.contributor.authorSouza, Samuel Xavier de
dc.contributor.authorAtienza, David
dc.date.accessioned2023-06-17T14:18:29Z
dc.date.available2023-06-17T14:18:29Z
dc.date.issued2019
dc.description©2019 IEEE IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)(27. 2019. Cuzco, Perú) ISSN 2324-8432 This work has been supported by Spanish MINECO (GA. No. TIN2015-65277-R), the Spanish MINECO (GA. No. S2018/TCS-4423), the SERI Seed Money project (GA No. SMG1702), the EC H2020 RECIPE project (GA No. 801137), and the ERC Consolidator Grant COMPUSAPIEN (GA No. 725657).
dc.description.abstractAccurate workload prediction and throughput estimation are keys in efficient proactive power and performance management of multi-core platforms. Although hardware performance counters available on modern platforms contain important information about the application behavior, employing them efficiently is not straightforward when dealing with time-varying applications even if they have iterative structures. In this work, we propose a machine learning-based framework for workload prediction and throughput estimation using hardware events. Our framework enables throughput estimation over various available system configurations, namely, number of parallel threads and operating frequency. In particular, we first employ workload clustering and classification techniques along with Markov chains to predict the next workload for each available system configuration. Then, the predicted workload is used to estimate the next expected throughput through a machine learning-based regression model. The comparison with state of the art demonstrates that our framework is able to improve Quality of Service (QoS) by 3.4x, while consuming 15% less power thanks to the more accurate throughput estimation.
dc.description.departmentSección Deptal. de Arquitectura de Computadores y Automática (Físicas)
dc.description.facultyFac. de Ciencias Físicas
dc.description.refereedTRUE
dc.description.sponsorshipUnión Europea. H2020
dc.description.sponsorshipMinisterio de Economía y Competitividad (MINECO)
dc.description.sponsorshipState Secretariat for Education, Research and Innovation (SERI)
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/60291
dc.identifier.doi10.1109/VLSI-SoC.2019.8920309
dc.identifier.isbn978-1-7281-3915-9
dc.identifier.officialurlhttp://dx.doi.org/10.1109/VLSI-SoC.2019.8920309
dc.identifier.relatedurlhttps://ieeexplore.ieee.org/
dc.identifier.urihttps://hdl.handle.net/20.500.14352/14038
dc.language.isoeng
dc.page.final216
dc.page.initial211
dc.page.total6
dc.publication.placeNueva York
dc.publisherIEEE
dc.relation.ispartofseriesIEEE-IFIP International Conference on VLSI and System-on-Chip
dc.relation.projectIDRECIPE (801137); COMPUSAPIEN (725657)
dc.relation.projectIDTIN2015-65277-R
dc.relation.projectIDSMG1702
dc.rights.accessRightsopen access
dc.subject.cdu004.8
dc.subject.keywordIngeniería
dc.subject.keywordEléctrica
dc.subject.keywordElectrónica
dc.subject.ucmInteligencia artificial (Informática)
dc.subject.unesco1203.04 Inteligencia Artificial
dc.titleA machine learning-based framework for throughput estimation of time-varying applications in multi-core servers
dc.typebook part
dspace.entity.typePublication
relation.isAuthorOfPublication8cfc18ec-4816-404d-982d-21dc07318c07
relation.isAuthorOfPublication.latestForDiscovery8cfc18ec-4816-404d-982d-21dc07318c07
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