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Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs

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dc.contributor.authorClemente Barreira, Juan Antonio
dc.contributor.authorMansour, Wassim
dc.contributor.authorAyoubi, Rafic
dc.contributor.authorSerrano, Felipe
dc.contributor.authorMecha López, Hortensia
dc.contributor.authorZiade, Haissam
dc.contributor.authorEl Falou, Wassim
dc.contributor.authorVelazco, Raoul
dc.date.accessioned2023-06-18T06:55:40Z
dc.date.available2023-06-18T06:55:40Z
dc.date.issued2016-01-01
dc.description.abstractThis letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.
dc.description.departmentDepto. de Arquitectura de Computadores y Automática
dc.description.facultyFac. de Informática
dc.description.refereedFALSE
dc.description.sponsorshipMinisterio de Educación, Cultura y Deportes
dc.description.sponsorshipMobility grant for professors and researchers "José Castillejo"
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/39057
dc.identifier.doihttp://0-dx.doi.org.cisne.sim.ucm.es/10.1016/j.neucom.2015.06.038
dc.identifier.issn0925-2312
dc.identifier.officialurlhttp://0-www.sciencedirect.com.cisne.sim.ucm.es/science/article/pii/S0925231215008760
dc.identifier.urihttps://hdl.handle.net/20.500.14352/24602
dc.journal.titleNeurocomputing
dc.language.isoeng
dc.page.final1609
dc.page.initial1606
dc.publisherElsevier
dc.relation.projectIDTIN2013-40968-P
dc.rights.accessRightsopen access
dc.subject.cdu004.032.26
dc.subject.cdu004.312
dc.subject.cdu004.052.3
dc.subject.keywordArtificial Neural Network (ANN)
dc.subject.keywordHopfield Neural Network (HNN)
dc.subject.keywordSingle Event Upset (SEU)
dc.subject.keywordSingle Event Transient (SET)
dc.subject.keywordFPGA
dc.subject.keywordFault tolerance
dc.subject.ucmHardware
dc.titleHardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs
dc.typejournal article
dc.volume.number171
dspace.entity.typePublication
relation.isAuthorOfPublication919b239d-a500-4adb-aacf-00206a2c1512
relation.isAuthorOfPublication2363ed06-f92b-4c10-bd9a-87ac2fcce006
relation.isAuthorOfPublication.latestForDiscovery919b239d-a500-4adb-aacf-00206a2c1512

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