Customized Nios II multi-cycle instructions to accelerate block-matching techniques
dc.conference.date | February 08, 2015 | |
dc.conference.place | San Francisco, California, United States | |
dc.conference.title | SPIE 9400, Real-Time Image and Video Processing 2015 | |
dc.contributor.author | González, Diego | |
dc.contributor.author | Botella Juan, Guillermo | |
dc.contributor.author | García Sánchez, Carlos | |
dc.contributor.author | Meyer Bäse, Anke | |
dc.contributor.author | Meyer Bäse, Uwe | |
dc.contributor.author | Prieto Matías, Manuel | |
dc.date.accessioned | 2023-06-18T07:19:29Z | |
dc.date.available | 2023-06-18T07:19:29Z | |
dc.date.issued | 2015-02-27 | |
dc.description.abstract | This study focuses on accelerating the optimization of motion estimation algorithms, which are widely used in video coding standards, by using both the paradigm based on Altera Custom Instructions as well as the efficient combination of SDRAM and On-Chip memory of Nios II processor. Firstly, a complete code profiling is carried out before the optimization in order to detect time leaking affecting the motion compensation algorithms. Then, a multi-cycle Custom Instruction which will be added to the specific embedded design is implemented. The approach deployed is based on optimizing SOC performance by using an efficient combination of On-Chip memory and SDRAM with regards to the reset vector, exception vector, stack, heap, read/write data (.rwdata), read only data (.rodata), and program text (.text) in the design. Furthermore, this approach aims to enhance the said algorithms by incorporating Custom Instructions in the Nios II ISA. Finally, the efficient combination of both methods is then developed to build the final embedded system. The present contribution thus facilitates motion coding for low-cost Soft-Core microprocessors, particularly the RISC architecture of Nios II implemented in FPGA. It enables us to construct an SOC which processes 50×50 @ 180 fps. | |
dc.description.department | Depto. de Arquitectura de Computadores y Automática | |
dc.description.faculty | Fac. de Informática | |
dc.description.refereed | TRUE | |
dc.description.status | pub | |
dc.eprint.id | https://eprints.ucm.es/id/eprint/31452 | |
dc.identifier.doi | 10.1117/12.2077104 | |
dc.identifier.officialurl | http://dx.doi.org/10.1117/12.2077104 | |
dc.identifier.uri | https://hdl.handle.net/20.500.14352/24977 | |
dc.journal.title | SPIE Proceedings | |
dc.language.iso | eng | |
dc.publisher | SPIE | |
dc.relation.projectID | TIN 2012/32180 | |
dc.rights.accessRights | open access | |
dc.subject.cdu | 004.932 | |
dc.subject.keyword | Computer Vision | |
dc.subject.keyword | Optical Flow | |
dc.subject.keyword | MPEG Compression | |
dc.subject.keyword | Block Matching algorithm | |
dc.subject.keyword | NIOS II | |
dc.subject.keyword | FPGA | |
dc.subject.keyword | Custom Instructions | |
dc.subject.keyword | Embedded Systems | |
dc.subject.ucm | Informática (Informática) | |
dc.subject.ucm | Hardware | |
dc.subject.unesco | 1203.17 Informática | |
dc.title | Customized Nios II multi-cycle instructions to accelerate block-matching techniques | |
dc.type | conference paper | |
dc.volume.number | 9400 | |
dspace.entity.type | Publication | |
relation.isAuthorOfPublication | f94b32c6-dff7-4d98-9c7a-00aad48c2b6a | |
relation.isAuthorOfPublication | d04764e1-9d18-42ae-a9e7-c55f9bd50934 | |
relation.isAuthorOfPublication | 5d3f6717-1495-4217-853c-8c9c75d56620 | |
relation.isAuthorOfPublication.latestForDiscovery | f94b32c6-dff7-4d98-9c7a-00aad48c2b6a |
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