Customized Nios II multi-cycle instructions to accelerate block-matching techniques

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dc.conference.dateFebruary 08, 2015
dc.conference.placeSan Francisco, California, United States
dc.conference.titleSPIE 9400, Real-Time Image and Video Processing 2015
dc.contributor.authorGonzález, Diego
dc.contributor.authorBotella Juan, Guillermo
dc.contributor.authorGarcía Sánchez, Carlos
dc.contributor.authorMeyer Bäse, Anke
dc.contributor.authorMeyer Bäse, Uwe
dc.contributor.authorPrieto Matías, Manuel
dc.date.accessioned2023-06-18T07:19:29Z
dc.date.available2023-06-18T07:19:29Z
dc.date.issued2015-02-27
dc.description.abstractThis study focuses on accelerating the optimization of motion estimation algorithms, which are widely used in video coding standards, by using both the paradigm based on Altera Custom Instructions as well as the efficient combination of SDRAM and On-Chip memory of Nios II processor. Firstly, a complete code profiling is carried out before the optimization in order to detect time leaking affecting the motion compensation algorithms. Then, a multi-cycle Custom Instruction which will be added to the specific embedded design is implemented. The approach deployed is based on optimizing SOC performance by using an efficient combination of On-Chip memory and SDRAM with regards to the reset vector, exception vector, stack, heap, read/write data (.rwdata), read only data (.rodata), and program text (.text) in the design. Furthermore, this approach aims to enhance the said algorithms by incorporating Custom Instructions in the Nios II ISA. Finally, the efficient combination of both methods is then developed to build the final embedded system. The present contribution thus facilitates motion coding for low-cost Soft-Core microprocessors, particularly the RISC architecture of Nios II implemented in FPGA. It enables us to construct an SOC which processes 50×50 @ 180 fps.
dc.description.departmentDepto. de Arquitectura de Computadores y Automática
dc.description.facultyFac. de Informática
dc.description.refereedTRUE
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/31452
dc.identifier.doi10.1117/12.2077104
dc.identifier.officialurlhttp://dx.doi.org/10.1117/12.2077104
dc.identifier.urihttps://hdl.handle.net/20.500.14352/24977
dc.journal.titleSPIE Proceedings
dc.language.isoeng
dc.publisherSPIE
dc.relation.projectIDTIN 2012/32180
dc.rights.accessRightsopen access
dc.subject.cdu004.932
dc.subject.keywordComputer Vision
dc.subject.keywordOptical Flow
dc.subject.keywordMPEG Compression
dc.subject.keywordBlock Matching algorithm
dc.subject.keywordNIOS II
dc.subject.keywordFPGA
dc.subject.keywordCustom Instructions
dc.subject.keywordEmbedded Systems
dc.subject.ucmInformática (Informática)
dc.subject.ucmHardware
dc.subject.unesco1203.17 Informática
dc.titleCustomized Nios II multi-cycle instructions to accelerate block-matching techniques
dc.typeconference paper
dc.volume.number9400
dspace.entity.typePublication
relation.isAuthorOfPublicationf94b32c6-dff7-4d98-9c7a-00aad48c2b6a
relation.isAuthorOfPublicationd04764e1-9d18-42ae-a9e7-c55f9bd50934
relation.isAuthorOfPublication5d3f6717-1495-4217-853c-8c9c75d56620
relation.isAuthorOfPublication.latestForDiscoveryf94b32c6-dff7-4d98-9c7a-00aad48c2b6a
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