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Ianus: an adaptive FPGA computer

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2006

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IEEE Computer Soc.
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Dedicated machines designed for specific computational algorithms can outperform conventional computers by several orders of magnitude. In this note we describe Ianus, a new generation FPGA based machine and its basic features: hardware integration and wide reprogrammability. Our goal is to build a machine that can fully exploit the performance potential of new generation FPGA devices. We also plan a software platform which simplifies its programming, in order to extend its intended range of application to a wide class of interesting and computationally demanding problems. The decision to develop a dedicated processor is a complex one, involving careful assessment of its performance lead, during its expected lifetime, over traditional computers, taking into account their performance increase, as predicted by Moore’s law. We discuss this point in detail.

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© 2016 IEEE. Artículo firmado por 20 autores. We wish to thank Piero Vicini, Alessandro Lonardo, Davide Rossetti and Sergio De Luca for very useful discussions. We also thank Liliana Arrachea, Pierpaolo Bruscolini, Kenneth Dawson, Giacomo Marchiori, Yamir Moreno Vega, Giorgio Parisi, Ilenia Pedron and Federico Ricci-Tersenghi for sharing with us interesting ideas. This work has been partially supported by DGA, MEC (BFM2003-C08532-C03, FIS04-5073-C04, FISES2004-01399, FPA04-2602) and the European Community’s Human Potential Programme, contracts HPRNCT-2002-00307 (DYGLAGEMEM) and HPRN-CT-2002-00319 (STIPCO).

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