Ianus: an adaptive FPGA computer

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dc.contributor.authorFernández Pérez, Luis Antonio
dc.contributor.authorMartín Mayor, Víctor
dc.contributor.authorMuñoz Sudupe, Antonio
dc.contributor.authorotros, ...
dc.date.accessioned2023-06-20T11:17:33Z
dc.date.available2023-06-20T11:17:33Z
dc.date.issued2006-01
dc.description© 2016 IEEE. Artículo firmado por 20 autores. We wish to thank Piero Vicini, Alessandro Lonardo, Davide Rossetti and Sergio De Luca for very useful discussions. We also thank Liliana Arrachea, Pierpaolo Bruscolini, Kenneth Dawson, Giacomo Marchiori, Yamir Moreno Vega, Giorgio Parisi, Ilenia Pedron and Federico Ricci-Tersenghi for sharing with us interesting ideas. This work has been partially supported by DGA, MEC (BFM2003-C08532-C03, FIS04-5073-C04, FISES2004-01399, FPA04-2602) and the European Community’s Human Potential Programme, contracts HPRNCT-2002-00307 (DYGLAGEMEM) and HPRN-CT-2002-00319 (STIPCO).
dc.description.abstractDedicated machines designed for specific computational algorithms can outperform conventional computers by several orders of magnitude. In this note we describe Ianus, a new generation FPGA based machine and its basic features: hardware integration and wide reprogrammability. Our goal is to build a machine that can fully exploit the performance potential of new generation FPGA devices. We also plan a software platform which simplifies its programming, in order to extend its intended range of application to a wide class of interesting and computationally demanding problems. The decision to develop a dedicated processor is a complex one, involving careful assessment of its performance lead, during its expected lifetime, over traditional computers, taking into account their performance increase, as predicted by Moore’s law. We discuss this point in detail.
dc.description.departmentDepto. de Física Teórica
dc.description.facultyFac. de Ciencias Físicas
dc.description.refereedTRUE
dc.description.sponsorshipDGA, MEC (Spain)
dc.description.sponsorshipEuropean Community’s Human Potential Programme
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/38334
dc.identifier.citation[1] J. Beetem, M. Dennau, D. Weingarten, The GF11 Supercomputer, Proceedings of the 12th International Symposium on Computer Architecture (1985) 108. [2] The APE Collaboration, Comp. Phys. Com., 57 (1989) 285. [3] R. Tripiccione, Comp. Phys. Com., 139 (2001) 55. [4] N. H. Christ, A. E. Terrano, IEEE Trans.Comput., 33 (1984) 344 -- P. A. Boyle, et al., IBM J. of Res. & Development 49 (2005) 351. [5] T. E. J. Makino, M. Taiji, D. Sugimoto, Astr. Journal, 480 (1997) 432. [6] A. Bartoloni, et al., Int. J. of Mod. Physics C, 4 (1993) 993. [7] A. T. Ogileski, Phys. Rev. B, 32 (1985) 7384. [8] R. Pearson, J. Richardson, D. Toussant, Inst. of Theoretical Physics, University of California, Santa Barbara Report NSF-ITP-81-139 (1981). [9] A. Cruz, J. Pech, A. Tarancón, P. Téllez, C.L. Ullod, C. Ungil, Comp. Phys. Com., 133 (2001) 165. [10] The RTN Collaboration, Procc. of CHEP 92, CERN 92-07. [11] A. Hoogland, J. Spaa, B. Selman, A. Compagner, J. Comp. Phys., 51 (1983) 250. [12] M. Mezard, G. Parisi, M. A. Virasoro, Spin Glass Theory and Beyond (World Scientific, Singapore 1997). [13] A. Gara, et al, IBM J. of Res. & Development, 49 (2005) 195 -- see also other papers in the special issue of the IBM J. of Res. & Development 49 number 2/3 (2005). [14] see for instance the ClearSpeed www site: www.clearspeed.com [15] J. Kahle, M. Suzuoki, Y. Masubuchi, Cell Microprocessor Briefing, San Francisco (2005) S. Mueller, et al., The vector floating-point unit in a synergistic processor element of a Cell processor, Proc. 17th Int. Symp. on Computer Arithmetic (2005) to appear. [16] M. Creutz, Microcanonical Monte Carlo Simulation, Phys. Rev. Lett., 50-19 (1993). [17] J. J. Ruiz-Lorenzo, C. L. Ullod, cond-mat/9812378, Computer Physics Communications, (125) 1-3 (2000) 210-220. [18] M. Creutz, Quantum Fields on the Computer (World Scientific, Singapore 1992). [19] G. Parisi, F. Rapuano. Phys. Lett. B., 157B, 301 (1985).
dc.identifier.doi10.1109/MCSE.2006.9
dc.identifier.issn1521-9615
dc.identifier.officialurlhttp://doi.org/10.1109/MCSE.2006.9
dc.identifier.relatedurlhttp://ieeexplore.ieee.org/
dc.identifier.relatedurlhttp://arxiv.org/abs/cond-mat/0507270v1
dc.identifier.urihttps://hdl.handle.net/20.500.14352/51924
dc.issue.number1
dc.journal.titleComputing in science & engineering
dc.language.isoeng
dc.page.final49
dc.page.initial41
dc.publisherIEEE Computer Soc.
dc.relation.projectIDBFM2003-C08532-C03
dc.relation.projectIDFIS04-5073-C04
dc.relation.projectIDFISES2004-01399
dc.relation.projectIDFPA04-2602
dc.relation.projectIDHPRNCT-2002-00307 (DYGLAGEMEM)
dc.relation.projectIDHPRN-CT-2002-00319 (STIPCO)
dc.rights.accessRightsopen access
dc.subject.cdu53
dc.subject.cdu51-73
dc.subject.keywordSpecial-puropose computer
dc.subject.keywordMonte-Carlo simulation
dc.subject.keywordParallel processor
dc.subject.keywordSpin
dc.subject.keywordSystem
dc.subject.keywordApe.
dc.subject.ucmFísica (Física)
dc.subject.ucmFísica-Modelos matemáticos
dc.subject.unesco22 Física
dc.titleIanus: an adaptive FPGA computer
dc.typejournal article
dc.volume.number8
dspace.entity.typePublication
relation.isAuthorOfPublication146096b1-5825-4230-8ad9-b2dad468673b
relation.isAuthorOfPublication061118c0-eadf-4ee3-8897-2c9b65a6df66
relation.isAuthorOfPublication33f82d50-c0e4-4628-a384-f8b256a4a84e
relation.isAuthorOfPublication.latestForDiscovery146096b1-5825-4230-8ad9-b2dad468673b
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