A fast and efficient technique to apply Selective TMR through optimization

Abstract

Fault tolerance is an important factor for circuits in critical applications, especially those working in harsh environments. There are many techniques to increase reliability of circuits, being those based on redundancy very popular. In this way, Triple Modular Redundancy (TMR) is frequently used, but it usually incurs high area costs. That is why other alternative techniques, as Selective TMR, are used in order to reduce this cost. In this technique, only a subset of registers is tripled, those that are more sensitive and produce a higher error rate in the circuit. However, the problem of these methodologies is the complexity of finding the optimal set of registers to triple, what usually leads to very high computation times. In this paper, a novel solution that improves Selective TMR is presented, based on the automatic and fast calculation of an initial partition prior to the optimization process. The solution has been tested on a real communication circuit, a Feed-Forward Equalizer.