Aviso: para depositar documentos, por favor, inicia sesión e identifícate con tu cuenta de correo institucional de la UCM con el botón MI CUENTA UCM. No emplees la opción AUTENTICACIÓN CON CONTRASEÑA
 

Reliability Improvement of Hardware Task Graphs via Configuration Early-fetch

dc.contributor.authorRamezani, Reza
dc.contributor.authorSedaghat, Yasser
dc.contributor.authorClemente Barreira, Juan Antonio
dc.date.accessioned2023-06-17T22:06:28Z
dc.date.available2023-06-17T22:06:28Z
dc.date.issued2017-04
dc.description.abstractThis study presents a technique to improve the reliability and the Mean Time to Failure (MTTF) of hardware task graphs running on reconfigurable computers. This tech- nique, which has been named Task Early-fetch, can be applied to a sequence of one or several applications, represented as task graphs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous task graph, plus increasing the redundancy level of the early-fetched tasks. Experimental results on actual task graphs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant task graphs, and the improvement is more significant when applying to fault- tolerant task graphs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at run-time and steers the execution of the running task graphs. It demonstrates that, with 0.03% consumption of FFs and LUTs and also 1.22% occupancy of BRAMs available on a Xilinx Virtex UltraScale XCVU095-2FFVA2104E FPGA, the required run-time computations can be carried out in negligible delays.
dc.description.departmentDepto. de Arquitectura de Computadores y Automática
dc.description.facultyFac. de Informática
dc.description.refereedTRUE
dc.description.sponsorshipMinisterio de Ciencia e Innovación (MICINN)
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/44680
dc.identifier.doi10.1109/TVLSI.2016.2631724
dc.identifier.issn1063-8210
dc.identifier.officialurlhttp://ieeexplore.ieee.org/document/7779146/
dc.identifier.urihttps://hdl.handle.net/20.500.14352/18073
dc.issue.number4
dc.journal.titleIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.language.isoeng
dc.page.final1420
dc.page.initial1408
dc.publisherThe Institute of Electrical and Electronics Engineers (IEEE)
dc.relation.projectIDTIN2013-40968-P
dc.rights.accessRightsopen access
dc.subject.keywordFPGAs
dc.subject.keywordReliability
dc.subject.keywordTask Graph
dc.subject.keywordScheduling
dc.subject.keywordEarly-fetch
dc.subject.keywordFault Tolerance
dc.subject.ucmFísica nuclear
dc.subject.ucmCircuitos integrados
dc.subject.ucmHardware
dc.subject.ucmElectrónica (Informática)
dc.subject.unesco2207 Física Atómica y Nuclear
dc.subject.unesco2203.07 Circuitos Integrados
dc.subject.unesco2203 Electrónica
dc.titleReliability Improvement of Hardware Task Graphs via Configuration Early-fetch
dc.typejournal article
dc.volume.number25
dspace.entity.typePublication
relation.isAuthorOfPublication919b239d-a500-4adb-aacf-00206a2c1512
relation.isAuthorOfPublication.latestForDiscovery919b239d-a500-4adb-aacf-00206a2c1512

Download

Original bundle

Now showing 1 - 1 of 1
Loading...
Thumbnail Image
Name:
FINAL VERSION.pdf
Size:
2.09 MB
Format:
Adobe Portable Document Format

Collections