Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors

Abstract

With the rise of edge computing and the advancement of cryptography and error correction codes, portable device processors are demanded to increase their efficiency to run different applications and algorithms. To improve the performance of microprocessors, manufacturers add coprocessors or custom instructions to execute specific operations. Two essential contributions related to the customization of the instruction set are presented in this article. The first is the operator’s improvement for Galoid-field (GF) arithmetic, where the polynomial reduction module is fully programmable using a new zero-padding technique. The second is resource sharing between different operators within the microprocessor. This paper additionally describes two programmable and area-efficient GF arithmetic logic units for soft-core processors. The logic utilization is reduced from 16.67% to 37.00% for the combinational solution and 35.59% to 88.38% for the sequential solution, in ranges from 4 to 64 bits, running on a Kintex-7T field-programmable gate array (FPGA).