Escribiendo código RTL con Rust
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2025
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Abstract
El objetivo de este Trabajo de Fin de Grado es explorar las posibilidades prácticas del lenguaje de programación de alto nivel Rust en el diseño de circuitos digitales, utilizando la biblioteca Rust-HDL. A través del desarrollo de proyectos concretos (como un sumador combinacional, un reconocedor de patrones y un multiplicador escalar secuencial) se pretende evaluar la eficacia de Rust como herramienta alternativa a los lenguajes tradicionales de descripción hardware, especialmente Verilog.
Para ello, se han implementado versiones equivalentes de cada uno de los diseños tanto en Rust-HDL como en Verilog, y se han realizado comparaciones en términos de consumo de recursos, tiempos de ejecución y facilidad de desarrollo.
Las herramientas utilizadas para el análisis incluyen simuladores como GTKWave y herramientas de síntesis como Yosys, además de herramientas propias del ecosistema Rust como ’cargo run’y ’cargo test’.
Este trabajo tiene como objetivo principal determinar si Rust puede considerarse una opción viable y eficiente para el diseño hardware a nivel profesional, especialmente en proyectos de mayor escala.
The objective of this Bachelor’s Thesis is to explore the practical capabilities of the low-level programming language Rust in the design of digital circuits, using the Rust-HDL library. Through the development of specific projects (such as a combinational adder, a pattern recognizer, and a sequential scalar multiplier) we aim to evaluate Rust’s effectiveness as an alternative to traditional hardware description languages, particularly Verilog. To this end, equivalent designs have been implemented in both Rust-HDL and Verilog, and comparisons have been made in terms of resource usage, execution time, and development ease. The analysis relies on tools such as GTKWave for simulation, Yosys for synthesis, and Rust’s own toolchain via ’cargo run’ and ’cargo test’. The main goal of this work is to assess whether Rust can be considered a viable and efficient option for professional-scale hardware design projects.
The objective of this Bachelor’s Thesis is to explore the practical capabilities of the low-level programming language Rust in the design of digital circuits, using the Rust-HDL library. Through the development of specific projects (such as a combinational adder, a pattern recognizer, and a sequential scalar multiplier) we aim to evaluate Rust’s effectiveness as an alternative to traditional hardware description languages, particularly Verilog. To this end, equivalent designs have been implemented in both Rust-HDL and Verilog, and comparisons have been made in terms of resource usage, execution time, and development ease. The analysis relies on tools such as GTKWave for simulation, Yosys for synthesis, and Rust’s own toolchain via ’cargo run’ and ’cargo test’. The main goal of this work is to assess whether Rust can be considered a viable and efficient option for professional-scale hardware design projects.
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Trabajo de Fin de Grado en Ingeniería de Computadores, Facultad de Informática UCM, Departamento de Arquitectura de Computadores y Automática, Curso 2024/2025













