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Single Event Upsets under 14-MeV Neutrons in a 28-nm SRAM-based FPGA in Static Mode

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dc.contributor.authorFabero Jiménez, Juan Carlos
dc.contributor.authorMecha López, Hortensia
dc.contributor.authorFranco Peláez, Francisco Javier
dc.contributor.authorClemente Barreira, Juan Antonio
dc.contributor.authorKorkian, Golnaz
dc.contributor.authorRey, Solenne
dc.contributor.authorCheymol, Benjamin
dc.contributor.authorBaylac, Maud
dc.contributor.authorHubert, Guillaume
dc.contributor.authorVelazco, Raoul
dc.date.accessioned2023-06-16T15:16:14Z
dc.date.available2023-06-16T15:16:14Z
dc.date.issued2020
dc.description.abstractA sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.
dc.description.departmentDepto. de Estructura de la Materia, Física Térmica y Electrónica
dc.description.departmentDepto. de Arquitectura de Computadores y Automática
dc.description.facultyFac. de Ciencias Físicas
dc.description.facultyFac. de Informática
dc.description.refereedTRUE
dc.description.sponsorshipMinisterio de Economía y Competitividad (MINECO)
dc.description.sponsorshipIRT Nanoelec
dc.description.statusinpress
dc.eprint.idhttps://eprints.ucm.es/id/eprint/59496
dc.identifier.doi10.1109/TNS.2020.2977874
dc.identifier.issn0018-9499
dc.identifier.officialurlhttps://ieeexplore.ieee.org/document/9020124
dc.identifier.relatedurlhttps://doi.org/10.1109/TNS.2020.2977874
dc.identifier.urihttps://hdl.handle.net/20.500.14352/6088
dc.journal.titleIEEE Transactions on Nuclear Science
dc.language.isoeng
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc
dc.relation.projectIDTIN2017-87237
dc.relation.projectIDANR-10-AIRT-05
dc.rightsAtribución-CompartirIgual 3.0 España
dc.rights.accessRightsopen access
dc.rights.urihttps://creativecommons.org/licenses/by-sa/3.0/es/
dc.subject.keywordFPGA
dc.subject.keywordneutron tests
dc.subject.keywordradiation hardness
dc.subject.keywordreliability
dc.subject.keywordsoft error.
dc.subject.ucmElectrónica (Física)
dc.subject.ucmRadiactividad
dc.subject.ucmCircuitos integrados
dc.subject.ucmElectrónica (Informática)
dc.subject.ucmElectrónica (Informática)
dc.subject.unesco2203.07 Circuitos Integrados
dc.subject.unesco2203 Electrónica
dc.subject.unesco2203 Electrónica
dc.titleSingle Event Upsets under 14-MeV Neutrons in a 28-nm SRAM-based FPGA in Static Mode
dc.typejournal article
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