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Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

dc.contributor.authorClemente Barreira, Juan Antonio
dc.contributor.authorFranco Peláez, Francisco Javier
dc.contributor.authorVilla, Francesca
dc.contributor.authorBaylac, Maud
dc.contributor.authorRamos Vargas, Pablo Francisco
dc.contributor.authorVargas Vallejo, Vanessa Carolina
dc.contributor.authorMecha López, Hortensia
dc.contributor.authorAgapito Serrano, Juan Andrés
dc.contributor.authorVelazco, Raoul
dc.date.accessioned2023-06-17T23:52:19Z
dc.date.available2023-06-17T23:52:19Z
dc.date.issued2016-08-16
dc.description© IEEE-Inst Electrical Electronics Engineers. This work was supported in part by the Spanish MCINN project TIN2013-40968-P, by the Secretaría de Educación Superior Ciencia Tecnología e Innovación del Ecuador (SENESCYT), and by the “José Castillejo” mobility grant for professors and researchers.
dc.description.abstractThis paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.
dc.description.departmentDepto. de Estructura de la Materia, Física Térmica y Electrónica
dc.description.departmentDepto. de Arquitectura de Computadores y Automática
dc.description.facultyFac. de Ciencias Físicas
dc.description.facultyFac. de Informática
dc.description.refereedTRUE
dc.description.sponsorshipMinisterio de Economía y Competitividad (MINECO)
dc.description.sponsorshipSecretaría de Educación Superior Ciencia Tecnología e Innovación del Ecuador (SENESCYT)
dc.description.sponsorshipPrograma "José Castillejo" para movilidad de profesores
dc.description.sponsorshipMinisterio de Educación, Cultura y Deporte (MECD), España
dc.description.statuspub
dc.eprint.idhttps://eprints.ucm.es/id/eprint/35304
dc.identifier.doi10.1109/TNS.2016.2522819
dc.identifier.issn0018-9499
dc.identifier.officialurlhttp://dx.doi.org/10.1109/TNS.2016.2522819
dc.identifier.relatedurlhttp://www.ieee.org
dc.identifier.urihttps://hdl.handle.net/20.500.14352/18945
dc.issue.number4
dc.journal.titleIEEE Transactions on Nuclear Science
dc.language.isoeng
dc.page.final2079
dc.page.initial2072
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc
dc.relation.projectIDTIN2013-40968-P
dc.rights.accessRightsopen access
dc.subject.cdu537
dc.subject.keywordCOTS
dc.subject.keywordLPSRAM
dc.subject.keywordNeutron tests
dc.subject.keywordradiation hardness
dc.subject.keywordreliability
dc.subject.keywordsoft error
dc.subject.keywordSRAM
dc.subject.keywordCMOS integrated
dc.subject.keywordPower supplies
dc.subject.keywordRandom access memory
dc.subject.ucmElectrónica (Física)
dc.subject.ucmOrdenadores
dc.subject.ucmRadiactividad
dc.subject.ucmElectrónica (Informática)
dc.subject.unesco1203 Ciencia de Los Ordenadores
dc.subject.unesco2203 Electrónica
dc.titleSingle Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons
dc.typejournal article
dc.volume.number63
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dspace.entity.typePublication
relation.isAuthorOfPublication919b239d-a500-4adb-aacf-00206a2c1512
relation.isAuthorOfPublication662ba05f-c2fc-4ad7-9203-36924c80791a
relation.isAuthorOfPublication2363ed06-f92b-4c10-bd9a-87ac2fcce006
relation.isAuthorOfPublication.latestForDiscovery919b239d-a500-4adb-aacf-00206a2c1512

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