Efectos de radiaciones en circuitos integrados digitales: orígenes, técnicas de mitigación y tests experimentales

Abstract

This work presents an approach to predict the error rate due to Single Event Upsets (SEU), which are errors changing de content of memory cells, occurring in programmable circuits as the consequence of the impact of an energetic particle (heavy ion, proton, neutron,...) present in the environment where the circuits operates (space, earth's atmosphere, nuclear plants,...). For a chosen application, the error-rate is predicted by combining the DUT (Device Under Test) static SEU cross-section obtained from experiments performed in particle accelerators, and the results of fault injection campaigns performed off-beam during which huge number of SEUs are injected during the execution of the studied application. This methodology will be illustrated for a processor and a SRAM-based FPGA