Microwave noise modeling of InP based MODFETs biased for low power consumption

Abstract

This paper presents the fabrication, experimental characterization and modeling of 0.15 mum gate-length lattice matched MODFETs based on InP technology. The variation of the drain noise temperature of the Pospieszalski model (T-D) with the applied bias has been investigated under very low power consumption conditions, and a noticeably complex dependence of this factor on the drain current has been observed, In fact, T-D can decrease with increasing drain currents, and suffers a strong increase as a function of the drain voltage even at very low values of the drain current. However, all of these effects can be qualitatively explained from physical considerations.